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PCIe LTSSM (Link Training and Status State Machine)

The Link Training and Status State Machine (LTSSM) is the heart of PCIe link initialization. Understanding LTSSM is critical for debugging link bring-up issues and validating PCIe implementations.

What is LTSSM?

LTSSM is a finite state machine that controls:

  • Link Detection - Finding a connected device
  • Link Training - Establishing communication parameters
  • Link Operation - Normal data transfer
  • Power Management - Low-power states
  • Recovery - Handling errors and retraining

LTSSM States Overview

stateDiagram-v2
    [*] --> Detect
    Detect --> Polling : Receiver Detected
    Polling --> Configuration : TS1/TS2 Exchange
    Configuration --> L0 : Link Configured
    L0 --> Recovery : Error/Retrain
    Recovery --> L0 : Success
    Recovery --> Configuration : Speed Change
    L0 --> L0s : ASPM Entry
    L0s --> L0 : Exit
    L0 --> L1 : ASPM/PM Entry
    L1 --> Recovery : Exit
    L0 --> L2 : Power Down
    L2 --> Detect : Wake
    Detect --> Disabled : Link Disable

Major LTSSM States

1. Detect State

Purpose: Determine if a device is connected on the other end of the link.

Sub-state Description
Detect.Quiet Initial state, receiver termination check
Detect.Active Actively checking for receiver presence

Key Activities: - Transmitter sends common mode voltage - Checks for 50Ω termination on receiver - If detected, transitions to Polling

Common Issues: - Stuck in Detect: Check termination, power rails - Intermittent detection: Signal integrity issues

2. Polling State

Purpose: Establish bit lock, symbol lock, and lane polarity.

Sub-state Description
Polling.Active Send TS1, achieve bit/symbol lock
Polling.Configuration Exchange TS1/TS2 for training
Polling.Compliance Compliance test mode
Polling.Speed Speed negotiation (Gen2+)

TS1/TS2 Ordered Sets: 

TS1 Structure:
├── COM symbol (K28.5)
├── Link Number
├── Lane Number
├── N_FTS (Fast Training Sequence count)
├── Data Rate Identifier
├── Training Control bits
└── TS Identifier

Key Activities: - Bit lock establishment (CDR locks to incoming data) - Symbol lock (K28.5 COM character detection) - Lane polarity detection and correction

3. Configuration State

Purpose: Configure link width and assign lane numbers.

Sub-state Description
Configuration.Linkwidth.Start Determine link width
Configuration.Linkwidth.Accept Accept proposed width
Configuration.Lanenum.Wait Wait for lane numbers
Configuration.Lanenum.Accept Accept lane assignments
Configuration.Complete Configuration done
Configuration.Idle Send Idle data

Key Activities: - Link width negotiation (x1, x2, x4, x8, x16) - Lane reversal handling - Lane-to-lane deskew

4. L0 State (Normal Operation)

Purpose: Normal link operation with full bandwidth.

Characteristics: - All lanes active - Full power consumption - Data transfer enabled - TLP/DLLP transmission

Exit Conditions: - Error → Recovery - ASPM request → L0s or L1 - Power management → L1, L2, L3

5. Recovery State

Purpose: Re-establish link after errors or speed changes.

Sub-state Description
Recovery.RcvrLock Reacquire bit/symbol lock
Recovery.RcvrCfg Reconfigure link
Recovery.Speed Speed change handling
Recovery.Idle Return to L0
Recovery.Equalization EQ for Gen3+

Common Triggers: - Bit errors exceeding threshold - Link retraining request - Speed change negotiation - Equalization adjustment

6. Power Management States

L0s (Standby)

  • Low-latency idle state
  • TX in electrical idle
  • Fast exit (~100ns typical)
  • Managed by hardware (ASPM)

L1 (Low Power)

  • Deeper power savings
  • Both TX and RX in low power
  • Longer exit latency (~1-4μs)
  • Software or hardware initiated
L1 Sub-state Power Savings Exit Latency
L1.0 Moderate ~1μs
L1.1 High ~4μs
L1.2 Highest ~10μs+

L2 (Auxiliary Power)

  • Link powered down
  • Only Vaux maintained
  • Used for wake events
  • Complete power removal
  • Full re-initialization required

LTSSM for Different Generations

Gen1/Gen2 Training

sequenceDiagram
    participant TX as Transmitter
    participant RX as Receiver

    TX->>RX: TS1 (2.5 GT/s)
    RX->>TX: TS1 (2.5 GT/s)
    Note over TX,RX: Bit lock, Symbol lock
    TX->>RX: TS2
    RX->>TX: TS2
    Note over TX,RX: Link configured
    TX->>RX: Idle
    RX->>TX: Idle
    Note over TX,RX: Enter L0

Gen3+ Training (with Equalization)

Gen3 and above require equalization due to higher channel loss:

sequenceDiagram
    participant DS as Downstream Port
    participant US as Upstream Port

    Note over DS,US: Phase 0 - Preset
    DS->>US: EQ TS1 (Preset)
    US->>DS: EQ TS1 (Preset)

    Note over DS,US: Phase 1 - DS TX EQ
    DS->>US: EQ TS1 (Coefficients)
    US->>DS: EQ TS1 (Feedback)

    Note over DS,US: Phase 2 - US TX EQ
    DS->>US: EQ TS1 (Feedback)
    US->>DS: EQ TS1 (Coefficients)

    Note over DS,US: Phase 3 - Done
    DS->>US: TS2
    US->>DS: TS2

Equalization Phases:

Phase Description Activities
0 Preset Apply initial TX settings
1 Downstream TX EQ DS port optimizes TX
2 Upstream TX EQ US port optimizes TX
3 Complete Final verification

LTSSM Debug Techniques

Common LTSSM Issues

Symptom Likely Cause Debug Approach
Stuck in Detect No termination, power issue Check DC levels, termination
Stuck in Polling CDR not locking, SI issues Eye diagram, jitter analysis
Stuck in Config Width mismatch, lane issues Check TS1/TS2 content
Recovery loops Marginal signal, errors BER testing, eye analysis
EQ failure Channel too lossy S-parameter analysis

Capturing LTSSM Transitions

Using Protocol Analyzer: 1. Set trigger on LTSSM state change 2. Capture TS1/TS2 ordered sets 3. Analyze training sequence timing 4. Check for unexpected transitions

Using Oscilloscope: 1. Probe TX and RX differentially 2. Trigger on Electrical Idle exit 3. Capture TS1/TS2 waveforms 4. Verify signaling levels and timing

Key Timing Parameters

Parameter Description Typical Value
tTX-IDLE-MIN Min TX idle time 20 ns
tTX-IDLE-SET Time to set TX idle 50 ns
tRX-ELECIDLE RX idle detect time 125 ns
N_FTS Fast Training Sequences 50-255
tRECOVERY Max recovery time 24 ms
tPOLLING Max polling time 24 ms

Validation Checklist

  • Device detected in all power-on sequences
  • Link trains to expected width (x1, x4, x8, x16)
  • Link trains to maximum supported speed
  • Lane reversal handled correctly
  • Lane polarity inversion handled
  • EQ completes successfully (Gen3+)

Recovery Validation

  • Link recovers from induced errors
  • Speed change works correctly
  • Recovery completes within timeout
  • No unexpected transitions to lower speed

Power Management Validation

  • L0s entry/exit works
  • L1 entry/exit works
  • L1 substates function correctly
  • Wake from L2 works
  • ASPM latency meets requirements

References

  • PCI Express Base Specification (publicly available overview sections)
  • PCI-SIG website: pcisig.com