DDR Eye Diagram Analysis¶

This guide covers comprehensive eye diagram analysis techniques for DDR memory interfaces using oscilloscopes, characterizing the timing and voltage margins that determine reliable data transfer.

Eye Diagram Fundamentals for DDR¶

DDR Eye Structure¶

Unlike serial links, DDR uses source-synchronous clocking with separate data (DQ) and strobe (DQS) signals:

DDR Eye Diagram (DQ referenced to DQS):

         ◀────────── 1 UI ──────────▶
    ┌────────────────────────────────┐
    │        ╱╲           ╱╲         │  ← VOH
    │       ╱  ╲         ╱  ╲        │
    │      ╱ EYE ╲      ╱    ╲       │
    │     ╱       ╲    ╱      ╲      │
    │────╱─────────╲──╱────────╲─────│  ← VREF
    │   ╱           ╲╱          ╲    │
    │  ╱                         ╲   │  ← VOL
    └────────────────────────────────┘
           ◀──────▶
          Eye Width
           (Setup + Hold)

Read vs Write Eye¶

Aspect	Read Eye	Write Eye
Source	DRAM output	Controller output
Clock Reference	DQS from DRAM	DQS from Controller
Probe Location	Controller side	DRAM side
Training	Read leveling	Write leveling

Equipment Requirements¶

Oscilloscope Specifications¶

DDR Gen	Min Bandwidth	Recommended BW	Sample Rate
DDR4-2400	4 GHz	6 GHz	20 GSa/s
DDR4-3200	6 GHz	8 GHz	25 GSa/s
DDR5-4800	8 GHz	12 GHz	40 GSa/s
DDR5-6400	12 GHz	16 GHz	50 GSa/s

Recommended Equipment¶

Oscilloscopes:

Keysight Infiniium MXR/EXR (6-16 GHz)
Tektronix MSO6/DPO70000 Series
Teledyne LeCroy WavePro HD (12-bit)

Probes:

Active differential probes for DQ/DQS
Low-loading probes to minimize signal impact
Interposer solutions for DIMM measurements

Oscilloscope Eye Configuration¶

Vertical Settings¶

Parameter	DQ Signal	DQS Signal
Scale	100-200 mV/div	200-300 mV/div
Offset	VREF level	0V (differential)
Coupling	DC	DC
Bandwidth	Full	Full

Horizontal Settings for Eye¶

Parameter	Setting
Time/Division	50-100 ps/div (1-2 UI visible)
Sample Rate	Maximum
Memory Depth	Moderate for fast accumulation

Clock Recovery for DDR¶

Key Setting: Use DQS as the clock reference

Parameter	Setting
Clock Source	DQS signal
Recovery Type	Explicit clock (DQS)
Data Rate	Match DDR speed

Read Eye Characterization¶

Read Eye Setup¶

Read Eye Measurement:

    DRAM  ════════════════════════ Controller
      │                                │
    DQ out ──────────────────────▶ DQ in
    DQS out ─────────────────────▶ DQS in
                    │
                    ▼
              Probe here for
              Read Eye measurement

Configuration Steps¶

Configure oscilloscope for eye diagram mode
Set DQS as clock reference
Trigger on DQS rising or falling edge
Probe DQ signal near controller
Enable eye accumulation (infinite persistence)
Accumulate 10,000+ waveforms minimum

Read Eye Measurements¶

Measurement	Description	DDR4 Typical	DDR5 Typical
Eye Height	Vertical opening	150-300 mV	120-250 mV
Eye Width	Horizontal opening	150-250 ps	80-150 ps
tDQSQ	DQ-DQS skew	<100 ps	<80 ps
Setup Margin	Time before DQS	>50 ps	>40 ps
Hold Margin	Time after DQS	>50 ps	>40 ps

Write Eye Characterization¶

Write Eye Setup¶

Write Eye Measurement:

    Controller ════════════════════════ DRAM
        │                                 │
    DQ out ────────────────────────▶ DQ in
    DQS out ───────────────────────▶ DQS in
                        │
                        ▼
                  Probe here for
                  Write Eye measurement

Write Eye Measurements¶

Measurement	Description	DDR4	DDR5
Eye Height	Vertical opening	200-400 mV	180-350 mV
Eye Width	Horizontal opening	180-280 ps	100-180 ps
tDS	DQ setup to DQS	>45 ps	>35 ps
tDH	DQ hold after DQS	>45 ps	>35 ps

Per-Bit Eye Analysis¶

Why Per-Bit Analysis?¶

Each DQ bit may have different:

Trace length (flight time)
Crosstalk exposure
Via quality
Package routing

Per-Bit Measurement Procedure¶

Capture eye for DQ[0]
Record eye height, width, margins
Repeat for each DQ bit (DQ[0] through DQ[7] or DQ[15])
Identify worst-case bit
Calculate statistics

Per-Bit Results Table¶

DQ Bit	Eye Height (mV)	Eye Width (ps)	Setup (ps)	Hold (ps)
DQ0	245	185	95	90
DQ1	238	178	88	90
DQ2	252	192	98	94
DQ3	230	172	85	87
...	...	...	...	...
Min	230	172	85	87

Training Correlation¶

Pre-Training Eye¶

Capture eye before training completes:

Shows raw channel quality
Identifies fundamental limitations
Baseline for training effectiveness

Post-Training Eye¶

Capture eye after training:

Shows optimized timing
Verifies training algorithm
Confirms margin improvement

Training Window Correlation¶

Training Window vs Eye:

    Training Sweep:    ◀─────────────────────▶
                            Valid Range

    Eye Opening:              ◀────────▶
                           Actual Margin

    Training should center DQS within valid range

Verification	Method
Centering	Compare trained delay to eye center
Range	Verify training explored full window
Margin	Confirm sufficient margin from edges

Temperature Corner Analysis¶

Temperature Effects on Eye¶

Temperature	Effect on Eye
Cold (0°C)	Timing shifts, different margins
Room (25°C)	Baseline reference
Hot (85°C)	Increased jitter, reduced margins
Very Hot (95°C+)	Significant margin reduction

Thermal Eye Measurement¶

Procedure:

Place DUT in thermal chamber
Connect probes (minimize thermal mass)
Allow 15+ minutes for stabilization
Capture eye diagram
Record temperature and measurements
Repeat at each corner

Expected Variations¶

Parameter	Cold to Hot Change
Eye Height	-10% to -20%
Eye Width	-15% to -25%
Timing Shift	5-15 ps

Margin Mapping (Shmoo)¶

2D Margin Plot¶

Shmoo Plot (Voltage vs Timing):

    Voltage
    (mV)
     +50 │▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓
     +30 │▓▓▓▓▓▓▓        ▓▓▓▓▓▓▓
     +10 │▓▓▓▓   PASS      ▓▓▓▓▓
     -10 │▓▓▓▓    REGION    ▓▓▓▓
     -30 │▓▓▓▓▓▓▓        ▓▓▓▓▓▓▓
     -50 │▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓
         └────────────────────────▶
          -50  -30  -10  +10  +30  +50
                  Timing (ps)

    ▓ = FAIL     (blank) = PASS

Creating Margin Maps¶

Method 1: Hardware Shmoo

Use controller's built-in margin testing
Sweep timing delay and voltage offset
Record pass/fail at each point

Method 2: Oscilloscope Eye

Use BER contour mode (if available)
Statistical eye analysis
Map margins at target BER

Eye Mask Testing¶

JEDEC Eye Mask¶

DDR specifications define minimum eye openings:

JEDEC Eye Mask (Simplified):

    ┌────────────────────────────────┐
    │                                │
    │      ┌────────────────┐        │
    │      │  KEEP-OUT ZONE │        │  Eye must
    │      │   (Inner Mask) │        │  not enter
    │      └────────────────┘        │  this region
    │                                │
    └────────────────────────────────┘

Mask Dimensions¶

Parameter	DDR4-3200	DDR5-4800
Min Eye Height	100 mV	80 mV
Min Eye Width	0.35 UI	0.35 UI
Mask Margin	Required	Required

Mask Test Procedure¶

Load appropriate JEDEC mask
Configure oscilloscope for eye mode
Accumulate sufficient waveforms
Record mask violations
Measure margin to mask edge

Common Issues and Troubleshooting¶

Eye Closure Issues¶

Symptom	Likely Cause	Solution
Horizontal closure	ISI, timing skew	Check trace matching
Vertical closure	Noise, crosstalk	Improve power integrity
Asymmetric eye	Rise/fall mismatch	Check driver settings
Double eye	Clock recovery issue	Verify DQS quality

Measurement Issues¶

Issue	Cause	Solution
Noisy eye	Probe grounding	Improve ground path
Jittery edges	Trigger instability	Use cleaner trigger source
Missing data	Wrong trigger	Verify command sequence
Inconsistent results	Temperature drift	Control environment

Best Practices¶

Oscilloscope Configuration¶

Practice	Rationale
Use DQS as clock reference	Source-synchronous measurement
Sufficient accumulation	Statistical confidence
Proper probe compensation	Accurate measurements
Document all settings	Reproducibility

Measurement Practices¶

Practice	Rationale
Measure all DQ bits	Find worst case
Multiple temperatures	Verify margin across range
Correlate to training	Verify algorithm effectiveness
Record conditions	Enable comparison

Reporting¶

Required Data¶

Eye diagram screenshots
Eye height and width measurements
Setup and hold margins
Per-bit analysis summary
Temperature corner results
Equipment and settings used

Pass/Fail Criteria¶

Measurement	DDR4 Criteria	DDR5 Criteria
Eye Height	≥100 mV	≥80 mV
Eye Width	≥0.35 UI	≥0.35 UI
Setup Margin	≥45 ps	≥35 ps
Hold Margin	≥45 ps	≥35 ps

High-Speed Validation - Waveform capture
Timing Parameters - JEDEC specifications
Initialization & Training - Training algorithms
Oscilloscope Fundamentals - Instrument basics

References¶

JEDEC DDR4 Specification (JESD79-4)
JEDEC DDR5 Specification (JESD79-5)
JEDEC Timing Measurement (JESD65)
Memory vendor design guides