DDR4 Architecture Fundamentals

Understanding DDR4 memory architecture is essential for validation engineers working with memory subsystems. This guide covers the internal organization, addressing, and basic operations of DDR4 SDRAM.

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Memory Organization

Hierarchical Structure

DDR4 memory is organized in a hierarchical structure:

┌─────────────────────────────────────────────────────────────┐
│                        DIMM Module                          │
├─────────────────────────────────────────────────────────────┤
│  ┌─────────────┐  ┌─────────────┐  ┌─────────────┐         │
│  │   Rank 0    │  │   Rank 1    │  │   Rank N    │   ...   │
│  └─────────────┘  └─────────────┘  └─────────────┘         │
└─────────────────────────────────────────────────────────────┘

┌─────────────────────────────────────────────────────────────┐
│                          Rank                               │
├─────────────────────────────────────────────────────────────┤
│  ┌──────────┐  ┌──────────┐  ┌──────────┐  ┌──────────┐    │
│  │Bank Grp 0│  │Bank Grp 1│  │Bank Grp 2│  │Bank Grp 3│    │
│  └──────────┘  └──────────┘  └──────────┘  └──────────┘    │
└─────────────────────────────────────────────────────────────┘

┌─────────────────────────────────────────────────────────────┐
│                       Bank Group                            │
├─────────────────────────────────────────────────────────────┤
│     ┌────────┐  ┌────────┐  ┌────────┐  ┌────────┐         │
│     │ Bank 0 │  │ Bank 1 │  │ Bank 2 │  │ Bank 3 │         │
│     └────────┘  └────────┘  └────────┘  └────────┘         │
└─────────────────────────────────────────────────────────────┘

Key Components

Component	Description
DIMM	Dual Inline Memory Module - physical module
Rank	Collection of DRAM chips that respond together to a command
Bank Group	DDR4 introduces bank groups for improved parallelism
Bank	Independent memory array with its own row buffer
Row	A row of memory cells (also called a "page")
Column	Individual addressable location within a row

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Bank Groups - DDR4 Innovation

Bank groups are a key DDR4 innovation that enables higher bandwidth by reducing timing constraints between operations to different groups.

Bank Group Benefits

graph LR
    subgraph "Bank Group 0"
        B0[Bank 0]
        B1[Bank 1]
    end

    subgraph "Bank Group 1"
        B2[Bank 2]
        B3[Bank 3]
    end

    MC[Memory Controller] --> B0
    MC --> B1
    MC --> B2
    MC --> B3

Key Advantage: Operations to different bank groups can be pipelined more efficiently:

Timing Parameter	Same Bank Group	Different Bank Groups
tCCD (Column-to-Column)	tCCD_L (Long)	tCCD_S (Short)
tRRD (Row-to-Row)	tRRD_L (Long)	tRRD_S (Short)

This allows the memory controller to achieve higher effective bandwidth by scheduling operations across different bank groups.

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Bank Structure

Each bank contains:

1. Row Address Decoder - Selects the row to activate
2. Memory Cell Array - Stores actual data
3. Sense Amplifiers - Amplify and hold row data
4. Column Address Decoder - Selects columns for read/write

┌─────────────────────────────────────────┐
│              Bank Structure              │
├─────────────────────────────────────────┤
│    Row Address ──▶ ┌─────────────────┐  │
│                    │  Row Decoder    │  │
│                    └────────┬────────┘  │
│                             │           │
│    ┌────────────────────────▼────────┐  │
│    │                                 │  │
│    │      Memory Cell Array          │  │
│    │      (Rows × Columns)           │  │
│    │                                 │  │
│    └────────────────┬────────────────┘  │
│                     │                   │
│    ┌────────────────▼────────────────┐  │
│    │      Sense Amplifiers           │  │
│    │      (Row Buffer / Page)        │  │
│    └────────────────┬────────────────┘  │
│                     │                   │
│    Column Address ──▶ ┌─────────────┐   │
│                       │Col Decoder  │   │
│                       └──────┬──────┘   │
│                              │          │
│                        Data I/O         │
└─────────────────────────────────────────┘

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Addressing

Address Components

Component	Bits (Typical)	Description
Bank Group	2 bits	Selects 1 of 4 bank groups
Bank	2 bits	Selects 1 of 4 banks within group
Row	14-18 bits	Selects row within bank
Column	10 bits	Selects starting column

Address Mapping Example

Physical Address: 0x1234_5678_9ABC

┌─────────┬──────┬─────────────┬────────────┐
│ Bank Grp│ Bank │    Row      │   Column   │
│  2 bits │2 bits│  16 bits    │  10 bits   │
└─────────┴──────┴─────────────┴────────────┘

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Basic Operations

ACTIVATE (ACT)

Opens a row within a bank, copying row contents to sense amplifiers.

sequenceDiagram
    participant MC as Memory Controller
    participant Bank as DRAM Bank

    MC->>Bank: ACTIVATE (Row Address)
    Note over Bank: Row decoder selects row
    Note over Bank: Sense amps detect & amplify
    Bank-->>MC: Row data in sense amps (tRCD)

Key Timing: After ACTIVATE, wait tRCD before READ/WRITE.

READ

Reads data from an already activated row.

sequenceDiagram
    participant MC as Memory Controller
    participant Bank as DRAM Bank

    Note over Bank: Row already activated
    MC->>Bank: READ (Column Address)
    Note over Bank: Column decoder selects
    Bank-->>MC: Data burst (after CL)

Key Timing: Data appears CL (CAS Latency) clock cycles after READ command.

WRITE

Writes data to an already activated row.

sequenceDiagram
    participant MC as Memory Controller
    participant Bank as DRAM Bank

    Note over Bank: Row already activated
    MC->>Bank: WRITE (Column Address)
    MC->>Bank: Write Data (after WL)
    Note over Bank: Data written to sense amps

Key Timing: Data must be provided WL (Write Latency) clock cycles after WRITE command.

PRECHARGE

Closes an open row, preparing the bank for a new ACTIVATE.

Key Timing: After PRECHARGE, wait tRP before next ACTIVATE.

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Data Transfer

Burst Length

DDR4 uses a burst length of 8 (BL8), transferring 8 data beats per access:

         CK  ─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─
              └─┘ └─┘ └─┘ └─┘ └─┘

        DQS  ─────┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌──
                  └─┘ └─┘ └─┘ └─┘ └─┘

         DQ  ─────┬─┬─┬─┬─┬─┬─┬─┬─┬────
                  │0│1│2│3│4│5│6│7│
                  └─┴─┴─┴─┴─┴─┴─┴─┘
                        BL8 burst

Data Width Calculation

For a x8 DDR4 device with BL8:

Data per access = 8 bits × 8 beats = 64 bits = 8 bytes

For a 64-bit wide DIMM (8 × x8 devices):

Data per access = 64 bits × 8 beats = 512 bits = 64 bytes = 1 cache line

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Page Policy

Open Page Policy

Keep row active for potential sequential accesses:

• Advantage: Fast access if next request hits same row
• Disadvantage: Higher power, potential bank conflict delays

Close Page Policy

Precharge immediately after access:

• Advantage: Lower latency for random access patterns
• Disadvantage: Always incurs tRCD on subsequent accesses

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Refresh

DRAM cells leak charge and must be periodically refreshed.

Parameter	Description	Typical Value
tREFI	Refresh interval	7.8 μs
tRFC	Refresh cycle time	350 ns (8Gb)

Refresh Overhead = tRFC / tREFI ≈ 4.5%

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DDR4 Specifications Summary

Parameter	DDR4-2133	DDR4-2400	DDR4-2666	DDR4-3200
Clock	1066 MHz	1200 MHz	1333 MHz	1600 MHz
Data Rate	2133 MT/s	2400 MT/s	2666 MT/s	3200 MT/s
Voltage	1.2V	1.2V	1.2V	1.2V
Prefetch	8n	8n	8n	8n

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Validation Considerations

Key Areas to Validate

• Bank group interleaving works correctly
• Row buffer hit/miss behavior
• Refresh timing compliance
• Burst ordering
• Address mapping verification

Common Issues

Issue	Symptom	Debug Approach
Bank conflict	Reduced bandwidth	Check access patterns
Page miss penalty	High latency	Verify page policy
Refresh stall	Periodic latency spikes	Monitor refresh timing

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Related Topics

• DDR Timing Parameters - Detailed timing guide
• DDR Initialization - Power-up and training
• DDR High-Speed Validation - Signal integrity

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References

• JEDEC JESD79-4 DDR4 SDRAM Standard
• Memory manufacturer datasheets (publicly available sections)