PCIe Jitter Analysis¶

This guide covers comprehensive jitter analysis techniques for PCI Express implementations using oscilloscopes and BERTs, decomposing timing variations to understand their sources and impact on system margin.

Jitter Fundamentals¶

What is Jitter?¶

Jitter is the deviation of a signal's timing from its ideal position. In serial links, jitter directly impacts the available timing margin for data recovery.

Ideal vs. Actual Timing:

    Ideal:    │    │    │    │    │    │    │
              ↓    ↓    ↓    ↓    ↓    ↓    ↓
    Actual:   │   │    │     │   │    │     │
              ◀─▶
              Jitter

Jitter Components¶

Component	Description	Bounded?
Total Jitter (TJ)	All jitter combined	No
Random Jitter (RJ)	Gaussian distribution (thermal, shot noise)	No
Deterministic Jitter (DJ)	Systematic, repeatable	Yes
Data-Dependent Jitter (DDJ)	ISI-related timing variation	Yes
Periodic Jitter (PJ)	Correlated to periodic source	Yes
Duty Cycle Distortion (DCD)	Asymmetric rise/fall	Yes
Bounded Uncorrelated Jitter (BUJ)	Non-Gaussian bounded	Yes

Jitter Relationship¶

TJ = DJ + n × RJ

Where:
  - TJ = Total Jitter at target BER
  - DJ = Deterministic Jitter (peak-to-peak)
  - RJ = Random Jitter (RMS)
  - n  = Multiplier based on BER (n ≈ 14.07 for BER = 10^-12)

Equipment for Jitter Measurement¶

Real-Time Oscilloscope¶

Capabilities:

Single-shot jitter capture
Time Interval Error (TIE) measurement
Jitter decomposition software
Protocol-correlated jitter analysis

Requirements by Generation:

PCIe Gen	Min Bandwidth	Sample Rate	Jitter Floor
Gen3	16 GHz	40 GSa/s	< 1 ps rms
Gen4	25 GHz	80 GSa/s	< 0.5 ps rms
Gen5	50 GHz	128 GSa/s	< 0.3 ps rms

Recommended Models:

Keysight Infiniium UXR with EZJIT software
Tektronix DPO70000SX with DPOJET
Teledyne LeCroy with JitterPro

Sampling Oscilloscope¶

Capabilities:

Very low intrinsic jitter (< 200 fs)
High-precision TIE measurement
Pattern-locked acquisition
Compliance-grade measurements

Recommended Models:

Keysight 86100D DCA-X with jitter module
Tektronix DSA8300 with 80SJNB software

BERT¶

Capabilities:

Bathtub curve (jitter margin)
Jitter injection for JTOL
Statistical confidence at low BER
Long-term jitter trending

Recommended Models:

Keysight M8040A/M8045A/M8050A
Anritsu MP1900A Signal Quality Analyzer

Oscilloscope Jitter Measurement¶

Time Interval Error (TIE)¶

TIE measures the deviation of each edge from its ideal position:

TIE Measurement:

    Reference:  │    │    │    │    │    │
                ↓    ↓    ↓    ↓    ↓    ↓
    Signal:     │   │    │     │   │    │
                └─┬─┘    └──┬──┘   └─┬──┘
                 TIE₁      TIE₂    TIE₃

    TIE = Actual Edge Time - Ideal Edge Time

Configuration:

Set clock recovery per specification
Capture long acquisition (100K+ edges)
Enable TIE measurement
Record TIE trend and histogram

Jitter Histogram Analysis¶

TIE Histogram:

    Count
      │
      │         ╱╲
      │        ╱  ╲
      │       ╱    ╲      ╱╲
      │      ╱      ╲    ╱  ╲
      │     ╱        ╲  ╱    ╲
      │    ╱          ╲╱      ╲
      └────────────────────────────▶ TIE (ps)
              ◀──────────────▶
                   TJ (pp)

    Dual peaks indicate DDJ or DCD
    Wide tails indicate RJ

Jitter Decomposition¶

Software Analysis Steps:

Capture TIE data (minimum 10^6 edges)
Apply tail-fit algorithm for RJ extraction
Separate DJ components (DDJ, PJ, DCD)
Calculate TJ at target BER

Decomposition Results Table:

Component	Value	Unit
TJ @ 10^-12	X.XX	UI pp
RJ	X.XX	UI rms
DJ	X.XX	UI pp
DDJ	X.XX	UI pp
PJ	X.XX	UI pp
DCD	X.XX	UI pp

BERT Jitter Measurement¶

Bathtub Curve Method¶

The BERT directly measures timing margin at target BER:

Bathtub Curve:

    BER
    │
10^-3┤▓▓▓▓                              ▓▓▓▓
     │    ▓▓                          ▓▓
10^-6┤      ▓▓                      ▓▓
     │        ▓▓                  ▓▓
10^-9┤          ▓▓              ▓▓
     │            ▓▓          ▓▓
10^-12┤             ▓▓▓▓▓▓▓▓▓▓
     └──┬───┬───┬───┬───┬───┬───┬───┬──
        0   0.125 0.25 0.375 0.5 0.625 0.75  1.0
                        UI

        ◀───────────────────▶
         Timing Margin @ 10^-12
         = 1 UI - TJ @ 10^-12

BERT Configuration for Jitter¶

Parameter	Setting
Scan resolution	64-128 points/UI
Dwell time	Sufficient for target BER
Pattern	PRBS for full stress
Clock recovery	Per specification

Q-Factor Extraction¶

From bathtub curve, extract Q-factor:

Q = (Sample Point - Edge) / σ

Where σ is the RMS jitter at that edge

BER = 0.5 × erfc(Q / √2)

Q-Factor	BER
6.36	10^-10
7.03	10^-12
7.65	10^-14

Jitter Tolerance (JTOL) Testing¶

What is JTOL?¶

Jitter tolerance measures the receiver's ability to track applied sinusoidal jitter without exceeding a BER threshold.

JTOL Test Setup¶

    BERT (Tx with SJ Injection) ════ DUT Rx ════ DUT Tx ════ BERT Rx
            │                                        │
    Sinusoidal Jitter                          Loopback
    at programmed frequency
    and amplitude

JTOL Measurement Procedure¶

Set jitter frequency to first test point
Set jitter amplitude to specification minimum
Increase amplitude until BER > threshold
Record maximum tolerated amplitude
Move to next frequency point
Repeat until all points measured
Plot and compare to mask

PCIe JTOL Mask¶

Gen4 JTOL Requirements:

Frequency	Minimum Tolerance
10 kHz	8 UI
100 kHz	4 UI
1 MHz	2 UI
10 MHz	0.4 UI
100 MHz	0.1 UI

JTOL Curve:

    Jitter
  Amplitude
    (UI)
      │╲
   8  ├─╲───────────────────
      │  ╲
   4  │   ╲
      │    ╲
   2  │     ╲
      │      ╲
   1  │       ╲
      │        ╲
  0.4 │         ╲────
      │              ╲
  0.1 │               ╲────────
      └──┬────┬────┬────┬────┬──▶
        10k  100k  1M  10M  100M
                Frequency (Hz)

    ─── = Specification minimum (mask)

Clock Jitter Measurement¶

Reference Clock Requirements¶

Parameter	PCIe Spec
Frequency	100 MHz ± 300 ppm
SSC Range	0 to -0.5% (down-spread)
SSC Rate	30-33 kHz
Jitter	Per specification

Clock Jitter Measurement Methods¶

Time Domain (Oscilloscope):

Capture clock with long acquisition
Measure period jitter or TIE
Calculate RMS and peak-to-peak
Decompose into components

Frequency Domain (Spectrum Analyzer/Oscilloscope FFT):

Measure phase noise spectral density L(f)
Integrate over specified frequency range
Convert to RMS jitter:

σ = (1 / 2πf₀) × √(2 × ∫L(f)df)

SSC Verification¶

Measurement	Method
Deviation	Modulation depth measurement
Rate	Modulation frequency
Profile	Triangle vs. other shapes

Phase Noise Analysis¶

Phase Noise Measurement¶

Phase Noise Plot:

    L(f)
   (dBc/Hz)
      │
   -80┤────╲
      │     ╲
  -100┤      ╲
      │       ╲
  -120┤        ╲─────────────
      │                      ╲
  -140┤                       ╲───────
      │
  -160┤                            ────
      └──┬────┬────┬────┬────┬────┬──▶
        100  1k   10k  100k  1M   10M
                Offset Frequency (Hz)

Converting Phase Noise to Jitter¶

Integration limits depend on specification:

Interface	Integration Range
PCIe Gen3	10 kHz to 1.5 MHz
PCIe Gen4	10 kHz to 1.5 MHz
PCIe Gen5	10 kHz to 2.5 MHz

Spread Spectrum Clock (SSC)¶

SSC Purpose¶

SSC spreads clock energy to reduce EMI peaks:

Without SSC:          With SSC:
    │                     │
    │  ╱╲                 │    ▃▄▅▆▅▄▃
    │ ╱  ╲                │   ▂        ▂
    │╱    ╲               │  ▁          ▁
    └──────▶              └──────────────▶
    Frequency             Frequency
    (Sharp peak)          (Spread spectrum)

SSC Verification with Oscilloscope¶

Measurements:

Parameter	Method	Spec
Deviation	Frequency vs. time	0 to -0.5%
Rate	Period of modulation	30-33 kHz
Profile	Deviation vs. time	Triangle

Procedure:

Capture clock for multiple SSC cycles
Measure instantaneous frequency
Plot frequency vs. time
Extract deviation, rate, profile

Jitter Specifications by Generation¶

PCIe Gen3 (8 GT/s)¶

Parameter	Specification
UI	125 ps
Tx TJ	0.30 UI max
Tx RJ	0.03 UI rms max
Rx JTOL	Per mask

PCIe Gen4 (16 GT/s)¶

Parameter	Specification
UI	62.5 ps
Tx TJ	0.28 UI max
Tx RJ	0.025 UI rms max
Rx JTOL	Per mask

PCIe Gen5 (32 GT/s)¶

Parameter	Specification
UI	31.25 ps
Tx TJ	0.26 UI max
Tx RJ	0.02 UI rms max
Rx JTOL	Per mask

Best Practices¶

Oscilloscope Jitter Measurement¶

Practice	Rationale
Sufficient samples	Statistical accuracy (>10^6 edges)
Proper clock recovery	Match specification CDR
Low-noise setup	Minimize measurement floor
Calibration	Verify instrument jitter floor
Controlled environment	Temperature stability

BERT Jitter Measurement¶

Practice	Rationale
Pattern lock verification	Valid measurement
Sufficient dwell time	Statistical confidence
Known good baseline	Reference comparison
Document settings	Reproducibility

Common Issues¶

Issue	Cause	Solution
High RJ	Noise pickup	Improve shielding
High PJ	Power supply noise	Filter supplies
High DDJ	ISI from channel	Improve equalization
High DCD	Driver asymmetry	Check Tx design
JTOL failure	CDR bandwidth	Verify CDR settings

Reporting¶

Required Measurements¶

TJ at target BER
RJ (rms)
DJ breakdown (DDJ, PJ, DCD)
Bathtub curve
JTOL results vs. mask
Clock jitter (if applicable)

Pass/Fail Criteria¶

Measurement	Pass Criteria
Tx TJ	≤ specification
Tx RJ	≤ specification
Rx JTOL	≥ mask at all points
Clock Jitter	≤ specification

High-Speed Validation - Waveform capture
Eye Diagram Analysis - Eye measurements
Oscilloscope Fundamentals - Instrument basics
BERT Fundamentals - BER testing

References¶

PCI-SIG CEM Specification
PCI-SIG Base Specification
JEDEC JESD65C (Jitter Measurement)
IEEE 802.3 (Jitter methodology)

PCIe Jitter Analysis¶

Jitter Fundamentals¶

What is Jitter?¶

Jitter Components¶

Jitter Relationship¶

Equipment for Jitter Measurement¶

Real-Time Oscilloscope¶

Sampling Oscilloscope¶

BERT¶

Oscilloscope Jitter Measurement¶

Time Interval Error (TIE)¶

Jitter Histogram Analysis¶

Jitter Decomposition¶

BERT Jitter Measurement¶

Bathtub Curve Method¶

BERT Configuration for Jitter¶

Q-Factor Extraction¶

Jitter Tolerance (JTOL) Testing¶

What is JTOL?¶

JTOL Test Setup¶

JTOL Measurement Procedure¶

PCIe JTOL Mask¶

Clock Jitter Measurement¶

Reference Clock Requirements¶

Clock Jitter Measurement Methods¶

SSC Verification¶

Phase Noise Analysis¶

Phase Noise Measurement¶

Converting Phase Noise to Jitter¶

Spread Spectrum Clock (SSC)¶

SSC Purpose¶

SSC Verification with Oscilloscope¶

Jitter Specifications by Generation¶

PCIe Gen3 (8 GT/s)¶

PCIe Gen4 (16 GT/s)¶

PCIe Gen5 (32 GT/s)¶

Best Practices¶

Oscilloscope Jitter Measurement¶

BERT Jitter Measurement¶

Common Issues¶

Reporting¶

Required Measurements¶

Pass/Fail Criteria¶

Related Topics¶

References¶