DDR4 Timing Parameters¶

Understanding DDR4 timing parameters is essential for memory validation, debug, and performance optimization. This guide covers the key timing parameters organized by command type.

Overview¶

DDR4 timing parameters define the minimum time intervals between operations to ensure reliable data transfer and memory cell integrity.

graph LR
    subgraph "Command Timing"
        ACT[ACTIVATE]
        RD[READ]
        WR[WRITE]
        PRE[PRECHARGE]
        REF[REFRESH]
    end

    ACT -->|tRCD| RD
    ACT -->|tRCD| WR
    RD -->|tRTP| PRE
    WR -->|tWR| PRE
    PRE -->|tRP| ACT
    PRE -->|tRP| REF

ACTIVATE Timing¶

ACTIVATE command opens a row within a bank. These parameters control ACTIVATE-related timing.

Row-to-Row Delays¶

Parameter	Description	Typical Value
tRRD_S	ACTIVATE to ACTIVATE (different bank groups)	4-6 tCK
tRRD_L	ACTIVATE to ACTIVATE (same bank group)	6-8 tCK
tFAW	Four ACTIVATE Window	20-40 ns

tRRD_S vs tRRD_L¶

Bank Group 0    Bank Group 1    Bank Group 2    Bank Group 3
     │               │               │               │
    ACT0            ACT1            ACT2            ACT3
     │◄──tRRD_S────►│◄──tRRD_S────►│◄──tRRD_S────►│

Operations to different bank groups use tRRD_S (shorter delay).

Bank Group 0: Bank 0    Bank Group 0: Bank 1
         │                      │
        ACT0                   ACT1
         │◄─────tRRD_L────────►│

Operations to same bank group use tRRD_L (longer delay).

tFAW - Four ACTIVATE Window¶

The tFAW parameter limits power consumption by restricting ACTIVATE frequency:

Time ──────────────────────────────────────────────────►

ACT0    ACT1    ACT2    ACT3              ACT4
 │       │       │       │                  │
 │◄───────────── tFAW ─────────────────►│
 │                                        │
 └── Only 4 ACTIVATEs allowed in tFAW ────┘
     5th ACTIVATE must wait until tFAW expires

ACTIVATE to READ/WRITE¶

Parameter	Description	Typical Value
tRCD	ACTIVATE to READ/WRITE delay	13-18 tCK
tRAS	ACTIVATE to PRECHARGE delay	32-39 tCK
tRC	ACTIVATE to ACTIVATE (same bank)	tRAS + tRP

      ACT ────────────────────────────────────── PRE ─────── ACT
       │                                          │           │
       │◄───────────── tRAS ────────────────────►│           │
       │                                          │◄── tRP ──►│
       │◄──────────────────── tRC ──────────────────────────►│
       │                                                      │
       │◄─ tRCD ─►│
                  RD/WR

REFRESH Timing¶

DRAM cells require periodic refresh to maintain data integrity.

Parameter	Description	Typical Value
tREFI	Average refresh interval	7.8 μs
tRFC	REFRESH cycle time	260-350 ns
tRP	PRECHARGE time before REFRESH	13-18 tCK

Refresh Sequence¶

All Banks       REFRESH                  Next Command
Precharged         │                          │
     │             │                          │
     │◄── tRP ────►│◄──────── tRFC ─────────►│

Refresh Modes¶

DDR4 supports flexible refresh scheduling:

Mode	Description	Postponable REFs
1x	Normal refresh	Up to 8
2x	Fine granularity	Up to 16
4x	Finest granularity	Up to 32

READ Timing¶

CAS Latency (CL)¶

The number of clock cycles from READ command to first data output.

Parameter	Description	Typical Value
CL	CAS Latency	14-22 tCK
AL	Additive Latency	0, CL-1, or CL-2
RL	Read Latency = CL + AL	-

    CK   ─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─
          └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘

   CMD   ──┬──────────────────────────────────────────
           │READ
           │

   DQS   ────────────────────────────┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌
                                     └─┘ └─┘ └─┘ └─┘ └─┘
           │◄──────── RL (CL+AL) ────►│
                                      │
    DQ   ────────────────────────────┬┬┬┬┬┬┬┬┬────────
                                     │D0-D7│

READ-to-READ Timing¶

Parameter	Description	Typical Value
tCCD_S	READ to READ (different bank groups)	4 tCK
tCCD_L	READ to READ (same bank group)	5-8 tCK

Different Bank Groups:
    RD0 ────► RD1 ────► RD2
     │◄─tCCD_S─►│◄─tCCD_S─►│

    DQ: ─────┬D0-D7┬─┬D0-D7┬─┬D0-D7┬────
             └─────┘ └─────┘ └─────┘
             (No gap - back-to-back bursts)

Clock-to-DQS Relationship¶

Parameter	Description
tDQSCK	DQS output edge to clock edge
tQSH	DQS high pulse width
tQSL	DQS low pulse width

DQS-to-DQ Relationship¶

Parameter	Description
tDQSQ	DQS edge to DQ valid (latest)
tQH	DQ hold time after DQS edge

   DQS   ─────────┬─────────┬─────────
                  │  ┌───┐  │
                  └──┘   └──┘

    DQ   ─────────╱ VALID ╲──────────
           ◄─tDQSQ─►│     │◄─tQH─►
                    Data Eye

WRITE Timing¶

CAS Write Latency (CWL)¶

The number of clock cycles from WRITE command to first data input.

Parameter	Description	Typical Value
CWL	CAS Write Latency	9-18 tCK
AL	Additive Latency	0, CL-1, or CL-2
WL	Write Latency = CWL + AL	-

    CK   ─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─
          └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘

   CMD   ──┬──────────────────────────────
           │WRITE
           │

   DQS   ────────────────────┐ ┌─┐ ┌─┐ ┌─┐ ┌─
                             └─┘ └─┘ └─┘ └─┘
           │◄───── WL ──────►│
                             │◄─tWPRE─►│
    DQ   ────────────────────┬─┬─┬─┬─┬─┬─┬─┬─
                             │D0│D1│D2│..│D7│

WRITE-to-WRITE Timing¶

Parameter	Description	Typical Value
tCCD_S	WRITE to WRITE (different bank groups)	4 tCK
tCCD_L	WRITE to WRITE (same bank group)	5-8 tCK

Clock-to-DQS Relationship (Write)¶

Parameter	Description
tDQSS	DQS input edge to clock edge
tDQSH	DQS high pulse width
tDQSL	DQS low pulse width

Write Preamble/Postamble¶

Parameter	Description
tWPRE	Write preamble (DQS driven low before burst)
tWPST	Write postamble (DQS driven high after burst)

PRECHARGE Timing¶

Parameter	Description	Typical Value
tRP	PRECHARGE to ACTIVATE	13-18 tCK
tRTP	READ to PRECHARGE	7.5 ns min
tWR	WRITE to PRECHARGE (write recovery)	15 ns
tWTR_S	WRITE to READ (different bank groups)	2.5 ns
tWTR_L	WRITE to READ (same bank group)	7.5 ns

Mode Register Timing¶

Parameter	Description	Typical Value
tMRD	MRS to MRS delay	8 tCK
tMOD	MRS to non-MRS command	24 tCK

Timing Parameter Quick Reference¶

ACTIVATE Parameters¶

Parameter	Full Name	When Used
tRRD_S	Row-to-Row Delay (Short)	ACT to ACT, different bank groups
tRRD_L	Row-to-Row Delay (Long)	ACT to ACT, same bank group
tFAW	Four ACTIVATE Window	Limits ACTIVATE rate
tRCD	RAS to CAS Delay	ACT to RD/WR
tRAS	Row Active Time	ACT to PRE minimum
tRC	Row Cycle Time	ACT to ACT same bank

READ/WRITE Parameters¶

Parameter	Full Name	When Used
CL	CAS Latency	RD cmd to data out
CWL	CAS Write Latency	WR cmd to data in
AL	Additive Latency	Posted command delay
RL	Read Latency (CL+AL)	Total read delay
WL	Write Latency (CWL+AL)	Total write delay
tCCD_S	Column-to-Column (Short)	RD/WR to RD/WR, different BG
tCCD_L	Column-to-Column (Long)	RD/WR to RD/WR, same BG

PRECHARGE/REFRESH Parameters¶

Parameter	Full Name	When Used
tRP	Row Precharge Time	PRE to ACT
tRTP	Read to Precharge	RD to PRE
tWR	Write Recovery	WR to PRE
tREFI	Refresh Interval	REF to REF average
tRFC	Refresh Cycle Time	REF to next command

Typical Values by Speed Grade¶

Parameter	DDR4-2133	DDR4-2400	DDR4-2666	DDR4-3200
tCK (ns)	0.938	0.833	0.750	0.625
CL	14	16	18	22
tRCD (ns)	13.13	13.33	13.5	13.75
tRP (ns)	13.13	13.33	13.5	13.75
tRAS (ns)	33	33	33	33
tRC (ns)	46.13	46.33	46.5	46.75
tRRD_S (tCK)	4	4	4	4
tRRD_L (tCK)	6	6	6	6
tCCD_S (tCK)	4	4	4	4
tCCD_L (tCK)	5	5	6	8
tFAW (ns)	25-35	23-30	21-30	21-30
tRFC (ns)	260-350	260-350	260-350	260-350

Validation Checklist¶

Timing Verification¶

CL/CWL programmed correctly for speed grade
tRCD/tRP meet minimum requirements
tRRD_S/tRRD_L correctly applied based on bank group
tFAW not violated under high ACTIVATE rate
tCCD_S/tCCD_L correctly applied
tREFI/tRFC refresh timing maintained
Write-to-Read turnaround (tWTR) correct

Common Timing Issues¶

Issue	Symptom	Debug Approach
tRCD violation	Read data corruption	Check ACT-to-RD timing
tWR violation	Write data loss	Verify WR-to-PRE timing
tFAW violation	Power/thermal issues	Monitor ACTIVATE rate
tREFI violation	Data retention failure	Check refresh scheduling

DDR Architecture - Memory organization
DDR Initialization - Training and calibration
DDR High-Speed Validation - Signal integrity

References¶

JEDEC JESD79-4 DDR4 SDRAM Standard
Memory manufacturer timing tables (publicly available)