LPDDR High-Speed Validation¶

This guide covers specialized high-speed validation techniques for LPDDR mobile memory interfaces using oscilloscopes, with advanced probing techniques to characterize signals in challenging package-on-package configurations.

Equipment Requirements¶

Oscilloscope Requirements by LPDDR Generation¶

LPDDR Gen	Data Rate	Min Bandwidth	Recommended BW	Min Sample Rate
LPDDR4-3200	3200 MT/s	6 GHz	8 GHz	25 GSa/s
LPDDR4X-4267	4267 MT/s	8 GHz	12 GHz	40 GSa/s
LPDDR5-6400	6400 MT/s	12 GHz	16 GHz	50 GSa/s
LPDDR5X-8533	8533 MT/s	16 GHz	20 GHz	80 GSa/s

Recommended Oscilloscopes¶

Real-Time Oscilloscopes:

Keysight Infiniium MXR/EXR Series (6-16 GHz)
Keysight Infiniium UXR (for highest speeds)
Tektronix MSO6/DPO70000 Series
Teledyne LeCroy WavePro HD (12-bit resolution)

Probing Challenges¶

LPDDR is typically in Package-on-Package (PoP) configuration:

PoP Configuration:

    ┌─────────────────────┐
    │      LPDDR Die      │  ← Memory on top
    └─────────────────────┘
            │ │ │
    ┌───────┴─┴─┴─────────┐
    │      SoC/AP Die     │  ← Application processor
    └─────────────────────┘
            │ │ │
    ═══════════════════════
           PCB

    No external access to memory signals!

Probing Solutions¶

Interposer Probing¶

Description: Custom PCB inserted between SoC and memory

Interposer Setup:

    ┌─────────────────────┐
    │      LPDDR Die      │
    └─────────────────────┘
            │ │ │
    ┌───────┴─┴─┴─────────┐
    │     Interposer      │ ◀── Probe points
    └─────────────────────┘
            │ │ │
    ┌───────┴─┴─┴─────────┐
    │      SoC/AP Die     │
    └─────────────────────┘

Advantages:

Access to all signals
Minimal signal degradation
Reusable for multiple tests

Challenges:

Custom design required
Added impedance and delay
May affect thermal behavior

Substrate Probing¶

Description: Direct probing of package substrate test points

Method	Description	Bandwidth
Solder-in probes	Permanent probe attachment	4-8 GHz
Flying probe	Temporary contact	2-4 GHz
Needle probe	Fine-pitch access	2-6 GHz

Non-Contact Probing¶

Method	Principle	Application
Capacitive	Electric field coupling	Low-frequency signals
Inductive	Magnetic field coupling	Current sensing
E-field	Near-field detection	Qualitative analysis

Design-for-Test (DFT)¶

Recommended DFT Features:

Dedicated probe points on substrate
Test vias to critical signals
Exposed pads for interposer attachment
Debug flex cable connections

Oscilloscope Configuration¶

Vertical Settings¶

Signal	Scale	Coupling	Notes
DQ	100-200 mV/div	DC	LPDDR has lower swing
WCK	150-250 mV/div	DC	Write clock
RDQS	150-250 mV/div	DC	Read strobe
CA	150-250 mV/div	DC	Command/address
CK	200-300 mV/div	DC	System clock

Horizontal Settings¶

Parameter	Setting
Time/Division	1-2 ns for timing, 50-100 ps for eye
Sample Rate	Maximum available
Memory Depth	Based on capture requirements
Trigger Position	10-20% for command capture

Data Signal (DQ) Characterization¶

DQ Waveform Capture¶

Key Measurements:

Measurement	LPDDR4/4X	LPDDR5/5X
VOH	VDDQ × 0.75	VDDQ × 0.75
VOL	VDDQ × 0.25	VDDQ × 0.25
Swing	240-400 mV	200-350 mV
Rise Time	<200 ps	<150 ps
Fall Time	<200 ps	<150 ps

Per-Byte Analysis¶

LPDDR typically uses x16 configuration (2 bytes):

Byte	DQ Bits	DQS/DMI
Byte 0	DQ[7:0]	DQS0/DMI0
Byte 1	DQ[15:8]	DQS1/DMI1

Clock Signal Analysis¶

WCK (Write Clock) - LPDDR5¶

LPDDR5 uses forwarded write clock instead of DQS for writes:

WCK Timing:

    CK   ────┬────────────┬────────────
             │            │
    WCK  ────────┬────┬────────┬────┬────
                 │    │        │    │
    DQ   ────────────┬────────────┬────
                     │            │
              Write Data aligned to WCK

WCK Measurements:

Parameter	LPDDR5 Specification
Frequency	2× to 4× CK frequency
Duty Cycle	45-55%
Differential Swing	200 mV min
tWCK2DQ	±0.25 tWCK

RDQS (Read Data Strobe)¶

RDQS Measurements:

Parameter	LPDDR5 Specification
Differential Swing	200 mV min
tDQSQ	DQ-RDQS skew
tQSH/tQSL	Strobe duty cycle

Read Timing Validation¶

Read Eye Diagram¶

Configuration:

Use RDQS as clock reference
Trigger on read command
Accumulate multiple bursts
Measure eye at controller

Read Timing Measurements¶

Parameter	Description	LPDDR5
tDQSCK	RDQS to CK	±200 ps
tDQSQ	DQ to RDQS	<80 ps
tQSH	RDQS high time	0.4 tCK min
tQSL	RDQS low time	0.4 tCK min

Write Timing Validation¶

Write Eye Diagram¶

Configuration:

Use WCK as clock reference (LPDDR5)
Use DQS as reference (LPDDR4)
Trigger on write command
Measure eye at DRAM

Write Timing Measurements¶

Parameter	Description	LPDDR5
tWCK2DQI	WCK to DQ	Per spec
tDS	DQ setup	35-50 ps
tDH	DQ hold	35-50 ps

Command/Address (CA) Validation¶

CA Bus Characteristics¶

Parameter	LPDDR4/4X	LPDDR5/5X
Bus Width	6 bits	7 bits
Data Rate	SDR	SDR or DDR
Voltage	VDDQ-based	VDD2-based

CA Timing Measurements¶

Parameter	Description	Typical
tIS	CA setup to CK	50-80 ps
tIH	CA hold after CK	50-80 ps
tCACD	CA to command delay	Per mode

Mobile-Specific Testing¶

Thermal Chamber Testing¶

Mobile devices operate across wide temperature range:

Condition	Temperature Range
Cold	-20°C to 0°C
Normal	25°C
Hot	85°C to 105°C

Procedure:

Mount DUT in thermal chamber
Route probes through chamber
Allow stabilization (15+ min)
Capture measurements
Compare margins across temperatures

DVFS (Dynamic Voltage Frequency Scaling)¶

Mobile devices change frequency/voltage dynamically:

Test Point	Frequency	Voltage
High Perf	Maximum	Nominal
Nominal	Mid	Nominal
Low Power	Reduced	Reduced

Measurement:

Capture eye at each DVFS point
Verify margins at all operating points
Check transitions between states

Power State Transitions¶

State	Description	Measurement
Active	Normal operation	Standard eye/timing
Self-Refresh	Low power state	Entry/exit timing
Power-Down	Minimum power	Wake-up sequence

Eye Diagram Analysis¶

Read Eye Measurement¶

LPDDR Read Eye:

    ◀────────── 1 UI ──────────▶
    ┌────────────────────────────┐
    │      ╱╲         ╱╲         │  ← VOH
    │     ╱  ╲       ╱  ╲        │
    │    ╱ EYE ╲    ╱    ╲       │
    │   ╱       ╲  ╱      ╲      │
    │──╱─────────╲╱────────╲─────│  ← VREF
    │ ╱                     ╲    │
    │╱                       ╲   │  ← VOL
    └────────────────────────────┘

Eye Measurements Summary¶

Measurement	LPDDR4X-4267	LPDDR5-6400
UI	234 ps	156 ps
Min Eye Height	80 mV	60 mV
Min Eye Width	0.35 UI	0.35 UI

Best Practices¶

Probing Best Practices¶

Practice	Rationale
Minimize probe loading	Preserve signal integrity
Short ground connections	Reduce inductance
Thermal management	Probe temperature effect
Document probe location	Reproducibility

Mobile-Specific Practices¶

Practice	Rationale
Test across temperature	Mobile thermal range
Verify all DVFS points	Dynamic operation
Check power state transitions	Mobile power management
Consider thermal throttling	Real-world behavior

Common Issues¶

Issue	Cause	Solution
No signal access	PoP configuration	Use interposer or DFT
Degraded signal	Probe loading	Use lower-capacitance probe
Timing variation	Temperature	Control thermal environment
Missing transitions	Trigger issues	Verify command sequence

Eye Diagram Analysis - Detailed eye measurement
LPDDR5 Architecture - LPDDR5 features
Oscilloscope Fundamentals - Instrument basics

References¶

JEDEC LPDDR4 Specification (JESD209-4)
JEDEC LPDDR5 Specification (JESD209-5)
Mobile device validation guides
Interposer design application notes