DDR High-Speed Validation¶

This guide covers comprehensive high-speed validation techniques for DDR memory interfaces using oscilloscopes, capturing and analyzing the critical DQ, DQS, and command signals that determine memory subsystem performance.

Equipment Requirements¶

Oscilloscope Requirements by DDR Generation¶

DDR Gen	Data Rate	Min Bandwidth	Recommended BW	Min Sample Rate
DDR4-2400	2400 MT/s	4 GHz	6 GHz	20 GSa/s
DDR4-3200	3200 MT/s	6 GHz	8 GHz	25 GSa/s
DDR5-4800	4800 MT/s	8 GHz	12 GHz	40 GSa/s
DDR5-6400	6400 MT/s	12 GHz	16 GHz	50 GSa/s
DDR5-8400	8400 MT/s	16 GHz	20 GHz	80 GSa/s

Recommended Oscilloscopes¶

Real-Time Oscilloscopes:

Keysight Infiniium MXR/EXR Series (6-16 GHz)
Keysight Infiniium UXR (for highest speeds)
Tektronix MSO6/DPO70000 Series
Teledyne LeCroy WavePro HD

Probing Solutions¶

Probe Type	Application	Bandwidth
Active Differential	DQ, DQS signals	8-20 GHz
Single-ended Active	CA, CLK signals	4-12 GHz
Solder-in	Production DFT	Varies
Interposer	DIMM interface	4-8 GHz

Recommended Probes:

Keysight N7020A (2 GHz, low loading)
Keysight InfiniiMax (8-20 GHz differential)
Tektronix P7700 Series

Oscilloscope Configuration¶

Vertical Settings¶

Signal	Scale	Coupling	Bandwidth
DQ	200-400 mV/div	DC	Full
DQS	200-400 mV/div	DC	Full
CLK	200-400 mV/div	DC	Full
CA	200-400 mV/div	DC	Full

Horizontal Settings¶

Parameter	Setting
Time/Division	1-2 ns for timing, 100 ps for eye
Sample Rate	Maximum available
Memory Depth	Sufficient for burst capture
Trigger Position	10-20% for command sequence

Trigger Configuration¶

Trigger Type	Application
Edge on CS#	Command capture
Pattern on CA	Specific command (ACT, RD, WR)
Edge on DQS	Data burst capture
Sequence	Command followed by data

Data Signal (DQ) Characterization¶

DQ Waveform Capture¶

DQ Signal Measurement Setup:

    Controller ════ DIMM/Device
        │             │
        └─────┬───────┘
              │
    Differential Probe ════ Oscilloscope

Key Measurements:

Measurement	Description	Typical Range
VOH	Output high voltage	VDDQ × 0.8
VOL	Output low voltage	VDDQ × 0.2
Vswing	Peak-to-peak voltage	400-600 mV
Rise Time	20-80% transition	< 200 ps
Fall Time	80-20% transition	< 200 ps

Per-Bit DQ Analysis¶

Procedure:

Capture DQ[0] through DQ[7] (or DQ[15] for x16)
Measure timing for each bit relative to DQS
Calculate setup and hold margins
Identify worst-case bits

Per-Bit Timing Table:

DQ Bit	tDQSQ (ps)	Eye Width (ps)	Eye Height (mV)
DQ0	XXX	XXX	XXX
DQ1	XXX	XXX	XXX
...	...	...	...

Strobe Signal (DQS) Analysis¶

DQS Waveform Capture¶

Differential DQS Measurement:

    DQS_t ────┬────
              │     Differential
    DQS_c ────┴──── Probe ════ Oscilloscope

Key Measurements:

Measurement	Description	DDR4	DDR5
Differential Swing	DQS_t - DQS_c	400 mV min	350 mV min
Crossing Point	50% crossing	VDDQ/2	VDDQ/2
Duty Cycle	High time / period	45-55%	47-53%
Rise/Fall Time	Edge rate	< 300 ps	< 200 ps

DQS-CLK Relationship¶

tDQSCK Measurement (Read):

              tDQSCK
         ◀─────────────▶
    CLK  ──────┬───────────────────
               │
    DQS  ──────────────┬───────────
                       │
    DQ   ──────────────────┬───────

Parameter	DDR4	DDR5
tDQSCK min	-225 ps	-180 ps
tDQSCK max	+225 ps	+180 ps

Write Timing Validation¶

Write Leveling Verification¶

Purpose: Verify DQS alignment to CLK at DRAM

Oscilloscope Setup:

Probe CLK at DRAM
Probe DQS at DRAM
Trigger on write command
Measure DQS-CLK relationship

Measurement:

Parameter	Description	Specification
tDQSS	DQS-CLK alignment	±0.25 tCK

Write DQ-DQS Timing¶

tDS (Setup) and tDH (Hold):

              tDS    tDH
           ◀──────▶◀────▶
    DQ   ──┬───────────────┬──
           │               │
    DQS  ──────────┬───────────
                   │
              DQS Edge

Parameter	DDR4-3200	DDR5-4800
tDS	45 ps	35 ps
tDH	45 ps	35 ps

Read Timing Validation¶

Read DQ-DQS Timing¶

tDQSQ Measurement:

              tDQSQ
           ◀────────▶
    DQS  ──────┬───────────────
               │
    DQ   ──────────┬───────────
                   │
              DQ Valid

Parameter	Description	DDR4	DDR5
tDQSQ max	DQ-DQS skew	100 ps	80 ps
tQH	DQ valid time	0.38 tCK	0.4 tCK

Read Eye Diagram¶

Configuration:

Trigger on DQS edge
Set horizontal scale for 1-2 UI
Enable eye diagram mode
Accumulate 10,000+ waveforms

Eye Measurements:

Measurement	Description
Eye Height	Vertical opening at center
Eye Width	Horizontal opening at crossing
Mask Margin	Distance to JEDEC mask

Eye Diagram Analysis¶

Read Eye Characterization¶

Oscilloscope Configuration:

Parameter	Setting
Clock Recovery	DQS as reference
UI	1/data rate
Accumulation	10,000+ waveforms
Persistence	Infinite or density

Write Eye Characterization¶

Note: Write eye is measured at controller output

Key Differences:

Aspect	Read Eye	Write Eye
Signal Source	DRAM	Controller
Reference	DQS from DRAM	DQS from Controller
Location	Near controller	Near DRAM

Eye Diagram Interpretation¶

DDR Eye Diagram:

           ◀──────── 1 UI ────────▶
    ┌──────────────────────────────┐
    │       ╱╲           ╱╲        │  ← VOH
    │      ╱  ╲         ╱  ╲       │
    │     ╱ EYE ╲      ╱    ╲      │
    │    ╱       ╲    ╱      ╲     │
    │───╱─────────╲──╱────────╲────│  ← Vref
    │  ╱           ╲╱          ╲   │
    │ ╱                         ╲  │  ← VOL
    └──────────────────────────────┘
         ◀────▶
       Eye Width

Command/Address (CA) Analysis¶

CA Signal Characterization¶

Parameter	DDR4	DDR5
VOH	VDDQ - 0.13V	VDD - 0.1V
VOL	0.13V	0.1V
tIS (setup)	65 ps	50 ps
tIH (hold)	90 ps	50 ps

CA Timing Measurement¶

Command Setup and Hold:

                tIS     tIH
             ◀──────▶◀──────▶
    CA   ────┬──────────────────┬────
             │                  │
    CLK  ────────────┬─────────────────
                     │
                CLK Rising Edge

Multi-Rank Timing¶

For multi-rank systems, verify timing to each rank:

Parameter	Description
CS# timing	Per-rank chip select
CA fanout	Signal integrity to all ranks
ODT timing	Termination control

Training Correlation¶

Write Leveling Verification¶

Post-Training Measurement:

Read trained delay values from controller
Measure actual DQS-CLK alignment
Correlate trained delays to measured timing

Read/Write Training Verification¶

Training	Oscilloscope Verification
Write Leveling	DQS-CLK at DRAM
Read Gate	DQS preamble detection
Read Leveling	DQ-DQS centering
Write Leveling	DQ-DQS centering

Temperature Analysis¶

Thermal Considerations¶

Temperature	Effect
Room (25°C)	Baseline measurement
Hot (85°C)	Increased timing variation
Cold (0°C)	Different timing behavior

Thermal Derating¶

DDR5 requires thermal derating above certain temperatures:

Temperature Range	Refresh Adjustment
0-85°C	Normal refresh
85-95°C	2× refresh rate
>95°C	4× refresh rate

Oscilloscope Thermal Testing¶

Place DUT in thermal chamber
Connect oscilloscope probes (minimize thermal impact)
Allow temperature stabilization
Capture measurements at each temperature point
Compare timing margins across temperatures

Common Measurements Summary¶

Read Path Measurements¶

Measurement	Method	Specification
tDQSCK	DQS to CLK	Per JEDEC
tDQSQ	DQ to DQS skew	Per JEDEC
tQH	DQ valid window	Per JEDEC
Read Eye	Eye diagram	Height/Width

Write Path Measurements¶

Measurement	Method	Specification
tDQSS	DQS to CLK	±0.25 tCK
tDS/tDH	DQ setup/hold	Per JEDEC
tDQS2DQ	DQS to DQ	Per JEDEC
Write Eye	Eye diagram	Height/Width

Best Practices¶

Oscilloscope Setup¶

Practice	Rationale
Calibrate probes	Accurate measurements
Minimize probe loading	Preserve signal integrity
Use proper grounding	Reduce noise
Set appropriate bandwidth	Avoid aliasing
Sufficient acquisitions	Statistical validity

Measurement Practices¶

Practice	Rationale
Consistent probe position	Reproducible results
Document test conditions	Correlation to specs
Measure all bits	Identify worst case
Temperature control	Valid comparisons

Common Issues¶

Issue	Cause	Solution
Noisy waveform	Ground loop	Improve probe grounding
Timing variation	Temperature drift	Stabilize DUT temperature
Missing transitions	Trigger issue	Adjust trigger level
Eye closure	ISI, crosstalk	Check channel quality

Eye Diagram Analysis - Detailed eye measurement
Timing Parameters - JEDEC timing specs
Initialization & Training - Training algorithms
Oscilloscope Fundamentals - Instrument basics

References¶

JEDEC DDR4 Specification (JESD79-4)
JEDEC DDR5 Specification (JESD79-5)
JEDEC Timing Measurement (JESD65)
Oscilloscope manufacturer application notes

DDR High-Speed Validation¶

Equipment Requirements¶

Oscilloscope Requirements by DDR Generation¶

Recommended Oscilloscopes¶

Probing Solutions¶

Oscilloscope Configuration¶

Vertical Settings¶

Horizontal Settings¶

Trigger Configuration¶

Data Signal (DQ) Characterization¶

DQ Waveform Capture¶

Per-Bit DQ Analysis¶

Strobe Signal (DQS) Analysis¶

DQS Waveform Capture¶

DQS-CLK Relationship¶

Write Timing Validation¶

Write Leveling Verification¶

Write DQ-DQS Timing¶

Read Timing Validation¶

Read DQ-DQS Timing¶

Read Eye Diagram¶

Eye Diagram Analysis¶

Read Eye Characterization¶

Write Eye Characterization¶

Eye Diagram Interpretation¶

Command/Address (CA) Analysis¶

CA Signal Characterization¶

CA Timing Measurement¶

Multi-Rank Timing¶

Training Correlation¶

Write Leveling Verification¶

Read/Write Training Verification¶

Temperature Analysis¶

Thermal Considerations¶

Thermal Derating¶

Oscilloscope Thermal Testing¶

Common Measurements Summary¶

Read Path Measurements¶

Write Path Measurements¶

Best Practices¶

Oscilloscope Setup¶

Measurement Practices¶

Common Issues¶

Related Topics¶

References¶