DDR4 Initialization and Training¶

DDR4 memory requires a careful initialization sequence and training procedures to establish reliable communication between the memory controller and DRAM devices. This guide covers the complete process from power-up to operational state.

Overview¶

DDR4 initialization involves multiple phases:

graph TD
    A[Power-Up] --> B[Reset Sequence]
    B --> C[Mode Register Initialization]
    C --> D[ZQ Calibration]
    D --> E[VrefDQ Training]
    E --> F[Write Leveling]
    F --> G[Read Training]
    G --> H[Write Training]
    H --> I[Operational State]

Power-Up Sequence¶

Voltage Ramp Requirements¶

DDR4 requires proper voltage sequencing:

Voltage	Specification	Typical Value
VDD	Core voltage	1.2V
VDDQ	I/O voltage	1.2V
VPP	DRAM array voltage	2.5V
VREF	Reference voltage	VDD/2 = 0.6V

Power-Up Timing¶

           ┌─────────────────────────────────
VDD/VDDQ   │
           │                ▲
───────────┘                │
                            │ VDD stable
                            ▼
           ┌─────────────────────────────────
VPP        │
           │                ▲
───────────┘                │
                            │ VPP stable
                            ▼
           ─────────────────┬───────────────
RESET#                      │
                            │◄── 200μs ──►│
                            │              │
                            │        RESET# high
                            ▼
           ──────────────────────────┬──────
CKE                                  │
                                     │◄─ 500μs ─►
                                     CKE high

Power-Up Steps¶

Apply VDD, VDDQ - Ramp to operating voltage
Apply VPP - Stable before CKE assertion
Assert RESET# - Hold low for at least 200μs after voltages stable
Release RESET# - De-assert RESET#
Wait tCKEsrx - Wait with CKE low
Assert CKE - Enable clocks and commands

Mode Register Initialization¶

DDR4 has seven Mode Registers (MR0-MR6) that configure device operation.

Mode Register Summary¶

Register	Key Settings
MR0	Burst Length, CAS Latency, DLL Reset
MR1	DLL Enable, Output Drive Strength, AL, Write Leveling
MR2	CAS Write Latency, Self-Refresh Temperature
MR3	MPR, Write CMD Latency, Fine Granularity Refresh
MR4	Maximum Power Down, Temperature Readout
MR5	CA Parity, CRC, Vref DQ Range
MR6	VrefDQ Training Value, tCCD_L

Initialization Sequence¶

sequenceDiagram
    participant MC as Memory Controller
    participant DRAM as DDR4 DRAM

    Note over MC,DRAM: After CKE high, wait tXPR
    MC->>DRAM: MRS (MR3) - MPR disable
    Note over MC,DRAM: Wait tMRD
    MC->>DRAM: MRS (MR6) - VrefDQ, tCCD_L
    Note over MC,DRAM: Wait tMRD
    MC->>DRAM: MRS (MR5) - CA Parity, Vref Range
    Note over MC,DRAM: Wait tMRD
    MC->>DRAM: MRS (MR4) - Temperature settings
    Note over MC,DRAM: Wait tMRD
    MC->>DRAM: MRS (MR2) - CWL
    Note over MC,DRAM: Wait tMRD
    MC->>DRAM: MRS (MR1) - Drive strength, AL
    Note over MC,DRAM: Wait tMRD
    MC->>DRAM: MRS (MR0) - CL, DLL Reset
    Note over MC,DRAM: Wait tMOD

ZQ Calibration¶

ZQ calibration adjusts the on-die termination (ODT) and output driver impedance.

ZQ Calibration Types¶

Type	Command	Duration	Usage
ZQCL	ZQ Calibration Long	tZQinit (1024 tCK)	After initialization
ZQCS	ZQ Calibration Short	tZQCS (128 tCK)	Periodic during operation

ZQ Calibration Sequence¶

         CMD ───┬───────────────────────────────────────────
                │ZQCL
                │
                │◄─────────── tZQinit ────────────────────►│
                │              (1024 tCK)                  │
                                                           │
                                               Next Command OK

When to Perform ZQ Calibration¶

After power-up initialization
After self-refresh exit
Periodically during operation (every 128ms typical)
After significant temperature change

VrefDQ Training¶

DDR4 uses internal Vref for DQ signals, which must be calibrated for optimal signal margin.

Vref Ranges¶

Range	MR6[6]	Voltage Range
Range 1	0	60% - 92.5% of VDDQ
Range 2	1	45% - 77.5% of VDDQ

Training Process¶

graph TD
    A[Start VrefDQ Training] --> B[Enter Training Mode]
    B --> C[Set Initial Vref Value]
    C --> D[Write Pattern]
    D --> E[Read Back and Compare]
    E --> F{Pass?}
    F -->|No| G[Adjust Vref]
    G --> C
    F -->|Yes| H[Record Passing Value]
    H --> I{Sweep Complete?}
    I -->|No| G
    I -->|Yes| J[Calculate Optimal Vref]
    J --> K[Program Optimal Value]
    K --> L[Exit Training Mode]

Training Steps¶

Enable Training Mode - Set MR3[2] = 1
Sweep Vref Values - Test range of Vref settings
Identify Pass/Fail Window - Find margin
Select Center Value - Choose optimal Vref
Program MR6 - Set final Vref value
Exit Training Mode - Set MR3[2] = 0

Write Leveling¶

Write leveling aligns the DQS strobe with the clock at the DRAM device.

Why Write Leveling?¶

Controller Side:                    DRAM Side:
    CK  ────────                    CK  ────────
    DQS ────────                    DQS ─────???
         │                               │
         │◄── Flight Time Skew ─────────►│

The clock (CK) and data strobe (DQS) have different routing paths, causing skew. Write leveling compensates for this.

Write Leveling Process¶

sequenceDiagram
    participant MC as Memory Controller
    participant DRAM as DDR4 DRAM

    MC->>DRAM: Enter Write Leveling (MR1)
    loop For each DQS
        MC->>DRAM: Drive DQS edge
        DRAM-->>MC: Sample CK, return on DQ
        Note over MC: Compare DQS-to-DQ timing
        Note over MC: Adjust DQS delay
    end
    MC->>DRAM: Exit Write Leveling

Algorithm¶

Enter Write Leveling Mode - Set MR1[7] = 1
Drive DQS Rising Edge
Sample CK at DRAM - DRAM samples CK on DQS edge
Read DQ Feedback - 0 = CK low, 1 = CK high
Find 0-to-1 Transition - Indicates DQS aligned to CK rising
Store Delay Value
Exit Write Leveling - Set MR1[7] = 0

Read Training¶

Read training determines the optimal sampling point for incoming read data.

Read Gate Training¶

Determines when to enable the DQS receiver:

    CK   ─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─
          └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘

   DQS   ──────────────┐ ┌─┐ ┌─┐ ┌─┐ ┌──
         (tri-state)   └─┘ └─┘ └─┘ └─┘
                       │◄─── Read Gate ───►│
                       Enable receiver here

Read DQS Centering¶

Centers the DQS sampling point within the DQ data eye:

    DQS   ─────────┬─────────┬─────────
                   │ Sample  │
                   │  Point  │
                   ▼         ▼
    DQ    ─────╱ VALID DATA ╲─────────
              │◄───────────►│
              Adjust to center

Training Algorithm¶

Issue READ Commands - Using known pattern (MPR mode)
Sweep DQS Delay - Find pass/fail boundaries
Calculate Window - Determine margin
Set Center Delay - Program optimal value

Write Training¶

Write training aligns write data timing for reliable writes.

Write DQ/DQS Training¶

Expected at DRAM:
    DQS   ─────────┬─────────┬─────────
                   │         │
    DQ    ─────────╲ DATA ╱─────────
                    Centered

Actual (before training):
    DQS   ─────────┬─────────┬─────────
                   │         │
    DQ    ───────────╲ DATA ╱───────
                      Offset!

Training Algorithm¶

Write Known Pattern
Read Back Data
Compare and Adjust - Sweep DQ delay relative to DQS
Find Passing Window
Program Center Value

Training Patterns¶

MPR (Multi-Purpose Register)¶

DDR4 provides MPR mode for training patterns:

MPR Page	Pattern
Page 0	01010101... (calibration)
Page 1	Complementary pattern
Page 2	User defined
Page 3	User defined

Enable MPR: Set MR3[2] = 1

Complete Initialization Sequence¶

┌─────────────────────────────────────────────────────────┐
│ 1. Power-Up (VDD, VDDQ, VPP ramp)                       │
├─────────────────────────────────────────────────────────┤
│ 2. Reset Sequence (RESET# low → high, CKE assertion)    │
├─────────────────────────────────────────────────────────┤
│ 3. Mode Register Programming (MR0-MR6)                  │
├─────────────────────────────────────────────────────────┤
│ 4. ZQ Calibration Long (ZQCL)                          │
├─────────────────────────────────────────────────────────┤
│ 5. Write Leveling                                       │
├─────────────────────────────────────────────────────────┤
│ 6. Read Gate Training                                   │
├─────────────────────────────────────────────────────────┤
│ 7. Read DQS Centering                                   │
├─────────────────────────────────────────────────────────┤
│ 8. Write DQ/DQS Training                                │
├─────────────────────────────────────────────────────────┤
│ 9. VrefDQ Training                                      │
├─────────────────────────────────────────────────────────┤
│ 10. Final ZQ Calibration Short (ZQCS)                  │
├─────────────────────────────────────────────────────────┤
│ 11. Normal Operation Ready                              │
└─────────────────────────────────────────────────────────┘

Validation Checklist¶

Initialization Verification¶

Power-up sequence timing correct
Reset timing meets specification
Mode registers programmed correctly
ZQ calibration completes successfully
DLL locks within specification

Training Verification¶

Write leveling achieves lock on all bytes
Read gate timing has adequate margin
Read DQS centering shows sufficient eye
Write training shows passing window
VrefDQ training finds optimal value

Common Issues¶

Issue	Symptom	Debug Approach
Training failure	Init timeout	Check SI, timing
Narrow margin	Intermittent errors	Adjust Vref, delays
Write leveling stuck	No 0-to-1 transition	Verify clock routing
Read gate failure	Data corruption	Adjust gate timing

DDR Architecture - Memory organization
DDR Timing Parameters - Timing reference
DDR High-Speed Validation - Signal integrity

References¶

JEDEC JESD79-4 DDR4 SDRAM Standard
Memory controller training documentation (publicly available)

DDR4 Initialization and Training¶

Overview¶

Power-Up Sequence¶

Voltage Ramp Requirements¶

Power-Up Timing¶

Power-Up Steps¶

Mode Register Initialization¶

Mode Register Summary¶

Initialization Sequence¶

ZQ Calibration¶

ZQ Calibration Types¶

ZQ Calibration Sequence¶

When to Perform ZQ Calibration¶

VrefDQ Training¶

Vref Ranges¶

Training Process¶

Training Steps¶

Write Leveling¶

Why Write Leveling?¶

Write Leveling Process¶

Algorithm¶

Read Training¶

Read Gate Training¶

Read DQS Centering¶

Training Algorithm¶

Write Training¶

Write DQ/DQS Training¶

Training Algorithm¶

Training Patterns¶

MPR (Multi-Purpose Register)¶

Complete Initialization Sequence¶

Validation Checklist¶

Initialization Verification¶

Training Verification¶

Common Issues¶

Related Topics¶

References¶