PCIe Eye Diagram Analysis¶

This guide covers comprehensive eye diagram analysis techniques for PCI Express implementations using oscilloscopes and BERTs, delivering statistical eye characterization and compliance verification essential for validation success.

Eye Diagram Fundamentals¶

What is an Eye Diagram?¶

An eye diagram is created by overlaying multiple bit periods of a serial data signal, revealing:

Voltage margins - Vertical eye opening
Timing margins - Horizontal eye opening
Signal quality - Noise, jitter, ISI effects
Transition behavior - Rise/fall characteristics

        Eye Diagram Structure

           Eye Height
              ↕
    ┌─────────────────────┐
    │   ╱╲       ╱╲       │  ← '1' Level
    │  ╱  ╲     ╱  ╲      │
    │ ╱    ╲   ╱    ╲     │
    │╱      ╲ ╱      ╲    │  ← Crossing Point
    │        ╳        ╲   │
    │       ╱ ╲        ╲  │
    │      ╱   ╲        ╲ │  ← '0' Level
    └─────────────────────┘
           ◀─────────▶
            Eye Width
              (UI)

Equipment for Eye Measurements¶

Real-Time Oscilloscope¶

Feature	Application
Single-shot capture	Non-repetitive signal analysis
Deep memory	Long pattern capture
Software eye	Constructed from captured data
Protocol decode	Correlated protocol/physical

Recommended Models:

Keysight Infiniium UXR (up to 110 GHz)
Tektronix DPO70000SX (up to 70 GHz)
Teledyne LeCroy LabMaster (up to 100 GHz)

Sampling Oscilloscope¶

Feature	Application
Low jitter	Precise timing measurements
High bandwidth	Very high-speed signals
Hardware eye	Built from repeated triggers
Compliance testing	Industry-standard method

Recommended Models:

Keysight 86100D DCA-X with appropriate modules
Tektronix DSA8300 with sampling modules

BERT (BER Contour)¶

Feature	Application
BER at each point	Statistical eye opening
Bathtub curves	Margin at target BER
2D eye scan	Complete margin map
Long-term testing	Very low BER verification

Recommended Models:

Keysight M8040A/M8045A/M8050A
Anritsu MP1900A Signal Quality Analyzer

Oscilloscope Eye Measurement¶

Configuration for Eye Diagram¶

Vertical Settings:

Parameter	Gen3/Gen4	Gen5	Gen6 (PAM4)
Scale	100-200 mV/div	100 mV/div	50 mV/div
Offset	Center	Center	Per eye level
Coupling	DC	DC	DC
Bandwidth	Full	Full	Full

Horizontal Settings:

Parameter	Setting
Time/div	1-2 UI span
Sample rate	Maximum
Memory	Sufficient for eye construction

Clock Recovery Settings¶

Clock recovery is critical for accurate eye measurement:

Parameter	PCIe Gen3	PCIe Gen4	PCIe Gen5
Loop BW	10 MHz	10 MHz	10 MHz
Peaking	Per spec	Per spec	Per spec
Reference	Explicit clock or CDR	Explicit or CDR	Explicit or CDR

Eye Accumulation¶

Minimum Acquisitions:

BER Target	Minimum Samples	Typical Time
10^-6	10^7	Seconds
10^-9	10^10	Minutes
10^-12	10^13	Hours

Best Practices:

Use infinite persistence or density mode
Enable automatic mask alignment
Allow sufficient accumulation time
Monitor for stability before measurement

BERT Eye Measurement (BER Contour)¶

How BERT Eye Works¶

The BERT measures BER at multiple sampling positions across the UI:

Sampling Point Scan:

    ─────────────────────────────────────
    │ •  •  •  •  •  •  •  •  •  •  •  │
    │ •  •  •  •  •  •  •  •  •  •  •  │
    │ •  •  •  .  .  .  .  .  •  •  •  │
    │ •  •  .  .  .  .  .  .  .  •  •  │
    │ •  •  .  .  .  .  .  .  .  •  •  │ Voltage
    │ •  •  .  .  .  .  .  .  .  •  •  │
    │ •  •  •  .  .  .  .  .  •  •  •  │
    │ •  •  •  •  •  •  •  •  •  •  •  │
    │ •  •  •  •  •  •  •  •  •  •  •  │
    ─────────────────────────────────────
                    Time (UI)

    • = High BER (>10^-6)    . = Low BER (<10^-12)

BERT Eye Configuration¶

Parameter	Setting
Horizontal resolution	64-128 points/UI
Vertical resolution	32-64 points
Dwell time per point	Based on target BER
Total scan time	Hours for 10^-12 contour

Bathtub Curve Measurement¶

Horizontal Bathtub (Timing):

    BER
    │
10^-3┤▓▓▓▓                              ▓▓▓▓
     │    ▓▓                          ▓▓
10^-6┤      ▓▓                      ▓▓
     │        ▓▓                  ▓▓
10^-9┤          ▓▓              ▓▓
     │            ▓▓          ▓▓
10^-12┤             ▓▓▓▓▓▓▓▓▓▓
     └──┬───┬───┬───┬───┬───┬───┬───┬──
        0  0.125 0.25 0.375 0.5 0.625 0.75 1.0
                        UI

           ◀────────────────▶
              Timing Margin
            at BER = 10^-12

Vertical Bathtub (Voltage):

Similar scan in voltage dimension at center of UI.

Compliance Mask Testing¶

PCIe Tx Eye Mask¶

The transmitter must produce an eye that does not violate the inner mask:

PCIe Eye Mask (Simplified):

    ┌─────────────────────────────────┐
    │                                 │
    │     ┌───────────────────┐       │
    │     │   KEEP-OUT ZONE   │       │  Eye must
    │     │    (Inner Mask)   │       │  stay outside
    │     └───────────────────┘       │  this region
    │                                 │
    └─────────────────────────────────┘

        ◀─────────────────────────▶
                   1 UI

Mask Parameters by Generation¶

Parameter	Gen3	Gen4	Gen5
Min Eye Height	80 mV	60 mV	45 mV
Min Eye Width	0.4 UI	0.35 UI	0.3 UI
Mask Margin	Required	Required	Required

Mask Test Procedure¶

With Oscilloscope:

Configure oscilloscope for PCIe measurement
Load appropriate compliance mask
Accumulate sufficient waveforms
Record mask margin and any violations
Document with screenshots and measurements

With BERT:

Configure BERT for 2D eye scan
Set resolution for desired accuracy
Run scan to target BER contour
Extract eye height/width at 10^-12
Compare to mask requirements

Key Eye Measurements¶

Eye Height¶

Definition: Vertical opening at the center of the eye (0.5 UI)

Oscilloscope Method:

Position measurement markers at 0.5 UI
Measure from top of '0' distribution to bottom of '1'
Statistical measurement accounts for noise

BERT Method:

Run vertical bathtub at UI center
Extract voltage range at target BER
Report as eye height at BER = 10^-X

Eye Width¶

Definition: Horizontal opening at the crossing level

Oscilloscope Method:

Position measurement at crossing amplitude
Measure from right edge of left crossing to left edge of right
Report in UI or picoseconds

BERT Method:

Run horizontal bathtub at threshold voltage
Extract timing range at target BER
Report as eye width at BER = 10^-X

Jitter Components in Eye¶

Component	Effect on Eye	Identification
Random Jitter (RJ)	Gaussian edge blur	Unbounded tails
Deterministic Jitter (DJ)	Discrete edge positions	Bounded peaks
ISI	Pattern-dependent closure	Bit history correlation
Crosstalk	Multi-modal distribution	Aggressor correlation

Receiver Eye Testing¶

Stressed Eye Input Test¶

Purpose: Verify receiver operates with worst-case input signal

Test Setup:

    BERT (Stressed Tx) ═══ Fixture ═══ DUT Rx
           │                              │
    Calibrated Stressed             Loopback to
         Eye Output                   BERT Rx

Stressed Eye Calibration¶

Parameter	Gen4 Spec	Gen5 Spec
Eye Height	15 mV min	12 mV min
Eye Width	0.3 UI min	0.25 UI min
SJ Amplitude	0.1 UI	0.08 UI
RJ (rms)	0.025 UI	0.02 UI

Calibration Steps:

Connect BERT output to reference oscilloscope
Verify clean signal amplitude
Add SJ, verify amplitude at specified frequency
Add RJ, verify RMS value
Enable ISI/channel filter
Measure composite eye meets specification

Pass Criteria¶

DUT must operate with BER < 10^-12
No loss of lock during test
Stable operation for specified duration

Corner Analysis¶

Voltage Corners¶

Corner	Condition	Expected Impact
Nominal	VDD = nominal	Baseline
Low Voltage	VDD - 5%	Reduced amplitude
High Voltage	VDD + 5%	Possible overshoot

Temperature Corners¶

Corner	Condition	Expected Impact
Room	25°C	Baseline
Hot	85-105°C	Increased jitter
Cold	0°C or -40°C	Timing shifts

Process Variation¶

For silicon characterization:

Test multiple devices (N ≥ 10)
Include fast, typical, slow process corners
Statistical analysis of margins

PAM4 Eye Analysis (Gen6)¶

Three-Eye Structure¶

Gen6 PCIe uses PAM4 signaling with four voltage levels:

    PAM4 Eye Diagram

    Level 3 ────╲    ╱────
                 ╲  ╱
    Level 2 ────╳╲╱╳────   ← Upper Eye
                ╱╲  ╱╲
    Level 1 ────╳╲╱╳────   ← Middle Eye
                ╱╲  ╱╲
    Level 0 ────╱──╲────   ← Lower Eye

PAM4-Specific Measurements¶

Measurement	Description
Eye Height (per eye)	Each of three eyes measured
Eye Linearity	Comparison of three eye heights
Level Separation	Uniformity of voltage levels
RLM	Ratio Level Mismatch metric

Best Practices¶

Oscilloscope Eye Measurement¶

Practice	Reason
Warm up instrument	Thermal stability
Calibrate before test	Measurement accuracy
Use proper probing	Signal integrity
Sufficient accumulation	Statistical validity
Document settings	Reproducibility

BERT Eye Measurement¶

Practice	Reason
Verify pattern lock	Valid measurement
Internal loopback test	Instrument verification
Appropriate resolution	Balance accuracy/time
Sufficient dwell time	Statistical confidence
Temperature control	Consistent conditions

Common Issues¶

Issue	Cause	Solution
Noisy eye	Probe grounding	Improve ground connection
Asymmetric eye	DC offset	Check coupling, offset
Double eye	Trigger issue	Verify clock recovery
Closed eye	Excessive loss	Check fixture, cables

Reporting¶

Required Data¶

Eye diagram screenshot (oscilloscope)
BER contour plot (BERT)
Eye height and width measurements
Mask margin values
Test conditions (voltage, temperature)
Equipment and settings used

Pass/Fail Criteria¶

Measurement	Pass Criteria
Mask Test	Zero violations
Eye Height	≥ specification minimum
Eye Width	≥ specification minimum
BER	< 10^-12 at eye center

High-Speed Validation - Waveform capture techniques
Jitter Measurement - Jitter decomposition
Oscilloscope Fundamentals - Instrument basics
BERT Fundamentals - BER testing

References¶

PCI-SIG CEM Specification
PCI-SIG Base Specification (Electrical)
IEEE 802.3 (eye measurement methodology)

PCIe Eye Diagram Analysis¶

Eye Diagram Fundamentals¶

What is an Eye Diagram?¶

Equipment for Eye Measurements¶

Real-Time Oscilloscope¶

Sampling Oscilloscope¶

BERT (BER Contour)¶

Oscilloscope Eye Measurement¶

Configuration for Eye Diagram¶

Clock Recovery Settings¶

Eye Accumulation¶

BERT Eye Measurement (BER Contour)¶

How BERT Eye Works¶

BERT Eye Configuration¶

Bathtub Curve Measurement¶

Compliance Mask Testing¶

PCIe Tx Eye Mask¶

Mask Parameters by Generation¶

Mask Test Procedure¶

Key Eye Measurements¶

Eye Height¶

Eye Width¶

Jitter Components in Eye¶

Receiver Eye Testing¶

Stressed Eye Input Test¶

Stressed Eye Calibration¶

Pass Criteria¶

Corner Analysis¶

Voltage Corners¶

Temperature Corners¶

Process Variation¶

PAM4 Eye Analysis (Gen6)¶

Three-Eye Structure¶

PAM4-Specific Measurements¶

Best Practices¶

Oscilloscope Eye Measurement¶

BERT Eye Measurement¶

Common Issues¶

Reporting¶

Required Data¶

Pass/Fail Criteria¶

Related Topics¶

References¶