PCIe High-Speed Validation¶

This guide covers comprehensive high-speed validation techniques for PCI Express implementations, utilizing real-time oscilloscopes, sampling oscilloscopes, and BERTs to characterize multi-gigabit signals across Gen3 through Gen6.

Equipment Requirements¶

Oscilloscope Requirements by Generation¶

PCIe Gen	Data Rate	Min Bandwidth	Recommended BW	Min Sample Rate
Gen3	8 GT/s	12 GHz	16 GHz	40 GSa/s
Gen4	16 GT/s	20 GHz	25 GHz	80 GSa/s
Gen5	32 GT/s	33 GHz	50 GHz	128 GSa/s
Gen6	64 GT/s (PAM4)	50 GHz	70+ GHz	256 GSa/s

BERT Requirements by Generation¶

PCIe Gen	Data Rate	BERT Requirement	Pattern Support
Gen3	8 GT/s	12+ Gbps	PRBS, Compliance
Gen4	16 GT/s	20+ Gbps	PRBS, Modified Compliance
Gen5	32 GT/s	40+ Gbps	PRBS23, Preset Patterns
Gen6	64 GT/s	64+ Gbaud PAM4	Gray-coded PRBS

Recommended Equipment¶

Real-Time Oscilloscopes:

Keysight Infiniium UXR (13-110 GHz)
Keysight Infiniium MXR (6-16 GHz)
Tektronix DPO70000SX (33-70 GHz)
Teledyne LeCroy LabMaster 10 Zi-A (36-100 GHz)

Sampling Oscilloscopes:

Keysight 86100D DCA-X with 86118A module
Tektronix DSA8300 with 80E11 module

BERTs:

Keysight M8040A/M8045A (64 Gbaud)
Keysight M8050A (120 Gbaud for Gen6)
Anritsu MP1900A Signal Quality Analyzer

Oscilloscope Configuration¶

Vertical Settings¶

Parameter	Gen3/Gen4	Gen5	Gen6
Scale	100-200 mV/div	100 mV/div	50-100 mV/div
Offset	Center signal	Center signal	Per-level for PAM4
Coupling	DC	DC	DC
Impedance	50Ω	50Ω	50Ω
Bandwidth	Full	Full	Full

Horizontal Settings¶

Parameter	Recommendation
Time/Division	5-10 UI for single-shot, 1-2 UI for eye
Sample Rate	Maximum available
Memory Depth	Maximum for long capture, reduce for eye
Trigger Position	10% for full packet capture

Trigger Configuration¶

Trigger Type	Application
Edge Trigger	Basic waveform capture
Pattern Trigger	TS1/TS2, SKP ordered set capture
Protocol Trigger	LTSSM state-based capture
Serial Pattern	Specific data pattern capture

Transmitter Testing with Oscilloscope¶

Output Amplitude Measurement¶

Measurement Setup:

    Tx ════╪════ Test Fixture ════ Oscilloscope
           │
    Reference Plane (TP2)

Procedure:

Configure oscilloscope for maximum bandwidth
Set vertical scale for signal to fill 60-80% of screen
Capture minimum 1000 UI for statistical accuracy
Measure differential peak-to-peak voltage (Vdiff-pp)

Specifications:

Gen	Vdiff-pp (min)	Vdiff-pp (max)
Gen3	800 mV	1300 mV
Gen4	800 mV	1300 mV
Gen5	800 mV	1200 mV

Rise/Fall Time Measurement¶

Measurement Points: 20% to 80% of signal amplitude

Gen	Rise Time (max)	Fall Time (max)
Gen3	45 ps	45 ps
Gen4	24 ps	24 ps
Gen5	12 ps	12 ps

Oscilloscope Requirements: Rise time measurement requires oscilloscope bandwidth ≥5× the equivalent signal bandwidth.

Pre-emphasis/De-emphasis Measurement¶

Coefficient Extraction from Waveform:

    Cursor (C0)      = Main tap amplitude
    Pre-cursor (C-1) = Amplitude one UI before transition
    Post-cursor (C+1)= Amplitude one UI after transition

    Ratio = 20 × log10(|C±1| / |C0|) dB

Preset Testing:

Preset	Pre-cursor (dB)	Post-cursor (dB)
P0	0	0
P1	0	-3.5
P2	0	-6.0
...	...	...

Transmitter Testing with BERT¶

BERT Tx Measurement Setup¶

    BERT (Pattern Generator) ════ Loopback ════ BERT (Error Detector)
                                     │
                               DUT in Path

For Tx Characterization:

    DUT Tx ════ Test Fixture ════ BERT Rx (Error Detector)
                     │
              Reference Plane

Pattern Selection¶

Test	Pattern	Purpose
Basic Verification	PRBS7	Quick functional check
Compliance Test	Modified Compliance Pattern	Specified Tx testing
Stress Test	PRBS23	Maximum ISI stress
Clock Recovery	PRBS31	CDR stress

Tx Compliance Measurements with BERT¶

Measurement	BERT Configuration
Output Amplitude	Measure Rx eye height
Jitter	TIE measurement mode
Data Rate	Frequency measurement
Preset Verification	Sweep all presets, measure each

Receiver Testing with BERT¶

Stressed Eye Calibration¶

The BERT generates a calibrated stressed eye signal per PCIe specification.

Gen4 Stressed Eye Parameters:

Parameter	Value
Eye Height	15 mV minimum
Eye Width	0.3 UI minimum
SJ	0.1 UI @ 10 MHz
RJ (rms)	0.025 UI
Total Jitter	0.55 UI max

Calibration Procedure:

Connect BERT output to calibration oscilloscope
Configure clean signal, verify amplitude
Add sinusoidal jitter (SJ), verify amplitude at specified frequency
Add random jitter (RJ), verify RMS value
Add ISI via channel or filter
Measure composite eye, verify against mask

Rx Sensitivity Testing¶

    BERT Tx (Stressed Eye) ════ Test Fixture ════ DUT Rx ════ DUT Tx ════ BERT Rx
                                                              (Loopback)

Procedure:

Calibrate stressed eye output
Connect to DUT receiver input
Configure DUT for internal loopback
Run BER measurement on BERT
Verify BER < 10^-12 (or specified threshold)

Jitter Tolerance (JTOL) Testing¶

JTOL Measurement with BERT:

Set BERT for sinusoidal jitter injection
Start at lowest test frequency (e.g., 100 kHz)
Increase jitter amplitude until BER exceeds threshold
Record maximum tolerated jitter
Step through frequency points per specification
Compare results to JTOL mask

PCIe Gen4 JTOL Template Points:

Frequency	Minimum Tolerance
100 kHz	4 UI
1 MHz	2 UI
10 MHz	0.4 UI
100 MHz	0.1 UI

Eye Diagram Analysis¶

Real-Time Oscilloscope Eye¶

Configuration:

Enable eye/mask mode
Set clock recovery bandwidth per specification
Accumulate minimum 10,000 waveforms
Enable BER contour analysis

Measurements:

Parameter	Description
Eye Height	Vertical opening at center
Eye Width	Horizontal opening at crossing
Mask Margin	Distance to mask boundary
Mask Hits	Number of violations

Sampling Oscilloscope Eye¶

Advantages:

Lower intrinsic jitter
Better for compliance testing
Hardware-based eye accumulation

Configuration:

Select appropriate clock recovery mode
Enable precision timebase
Run until statistical confidence achieved

BERT Eye (BER Contour)¶

2D BER Scan:

    Voltage
      ↑
      │  ▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓
      │  ▓▓▓         ▓▓▓▓▓
      │  ▓▓   10^-12  ▓▓▓▓
      │  ▓▓    eye    ▓▓▓▓
      │  ▓▓▓         ▓▓▓▓▓
      │  ▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓
      └─────────────────────▶ Time

    Each point: BER measured at that sampling position

BERT Bathtub Curve:

Provides timing margin at target BER (10^-12 typically).

Reference Clock Analysis¶

Oscilloscope Measurements¶

Measurement	Method	Specification
Frequency	Counter mode	100 MHz ±300 ppm
Amplitude	Peak-to-peak	Per clock type
SSC Deviation	Modulation measurement	Down-spread 0-0.5%
SSC Frequency	Modulation rate	30-33 kHz

Jitter Measurement¶

Phase Noise Method:

Use spectrum analyzer or oscilloscope FFT
Measure phase noise spectral density
Integrate over frequency range per spec
Convert to RMS jitter

TIE Method:

Capture long acquisition with oscilloscope
Measure Time Interval Error (TIE)
Calculate RMS and peak-to-peak jitter
Decompose into RJ, DJ components

Protocol-Triggered Acquisition¶

LTSSM State Capture¶

State	Trigger Pattern	Use Case
Detect	Electrical idle exit	Link initialization
Polling	TS1/TS2 patterns	Link training debug
Configuration	Link/Lane numbers	Width negotiation
L0	Data packets	Normal operation
Recovery	TS1/TS2	Link retraining

Ordered Set Triggering¶

Ordered Set	Pattern	Application
TS1	Training sequence	Link training
TS2	Training sequence	Link configuration
SKP	Skip ordered set	Clock compensation
EIEOS	Electrical idle exit	State transition

Measurement Best Practices¶

Oscilloscope Best Practices¶

Practice	Rationale
Calibrate before testing	Ensure measurement accuracy
Use proper probes	Active differential probes for high-speed
Minimize probe loading	Verify probe capacitance impact
De-embed fixtures	Remove fixture effects from measurement
Verify trigger stability	Ensure consistent capture point

BERT Best Practices¶

Practice	Rationale
Internal loopback first	Verify BERT operation
Calibrate stressed eye	Ensure specification compliance
Sufficient bit count	Statistical confidence
Monitor pattern sync	Verify valid measurement
Document all settings	Reproducibility

Common Issues and Solutions¶

Issue	Cause	Solution
Noisy eye	Ground loop, probe issue	Improve grounding, check probe
Unstable trigger	Low signal amplitude	Adjust trigger level, use holdoff
Mask failures	Fixture effects	De-embed fixture response
BER floor	Instrument noise	Reduce BERT amplitude, improve isolation
Pattern sync loss	Frequency mismatch	Verify clock source configuration

Test Configurations¶

Tx Compliance Test¶

    DUT ════╪════ Compliance Test Fixture ════ Oscilloscope/BERT
            │
     TP2 Reference Plane

Rx Sensitivity Test¶

    BERT (Stressed Tx) ════ Compliance Fixture ════ DUT Rx
                                                      │
                                              DUT Tx ═╪═ BERT Rx
                                                      │
                                               TP2 Reference

Channel Insertion Loss Test¶

    BERT Tx ════ Channel Under Test ════ BERT Rx
                        │
              Measure end-to-end BER

Eye Diagram Analysis - Statistical eye characterization
Jitter Measurement - Jitter decomposition techniques
S-Parameter Analysis - Channel characterization
Oscilloscope Fundamentals - Instrument operation
BERT Fundamentals - BER testing basics

References¶

PCI-SIG CEM Specification
PCI-SIG Base Specification
Oscilloscope and BERT manufacturer application notes